View D780206GF_490148.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

User's Manual
PD780208 Subseries
8-Bit Single-Chip Microcontrollers
PD780204 PD780204A PD780205 PD780205A PD780206 PD780208 PD78P0208
Document No. U11302EJ4V0UM00 (4th edition) Date Published July 2003 N CP(K) c Printed in Japan
[MEMO]
2
User's Manual U11302EJ4V0UM
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
FIP and IEBus are trademarks of NEC Electronics Corporation. MS-DOS, Windows, and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. TRON stands for The Realtime Operating system Nucleus. ITRON is an abbreviation of Industrial TRON.
User's Manual U11302EJ4V0UM
3
These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited.
* The information in this document is current as of January, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1
4
User's Manual U11302EJ4V0UM
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [GLOBAL SUPPORT] http://www.necel.com/en/support/support.html
NEC Electronics America, Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782
NEC Electronics (Europe) GmbH
Duesseldorf, Germany Tel: 0211-65 03 01 * Sucursal en Espana Madrid, Spain Tel: 091-504 27 87 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 * Filiale Italiana Milano, Italy Tel: 02-66 75 41 * Branch The Netherlands Eindhoven, The Netherlands Tel: 040-244 58 45 * Tyskland Filial Taeby, Sweden Tel: 08-63 80 820 * United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318
NEC Electronics Hong Kong Ltd.
Seoul Branch Seoul, Korea Tel: 02-558-3737
NEC Electronics Shanghai, Ltd.
Shanghai, P.R. China Tel: 021-6841-1138
NEC Electronics Taiwan Ltd.
Taipei, Taiwan Tel: 02-2719-2377
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 6253-8311
J03.4
User's Manual U11302EJ4V0UM
5
Major Revisions in This Edition
Page Throughout Description Addition of the following products to target products * PD780204A * PD780205A Deletion of the following package from target products * PD78P0208KL-T (100-pin ceramic WQFN) p.29 p.32 p.33 CHAPTER 1 OUTLINE * Update of 1.6 78K/0 Series Lineup * Addition of Note in 1.8 Overview of Functions * Addition of Caution in Table 1-1 Mask Options in Mask ROM Versions CHAPTER 2 PIN FUNCTIONS * Addition of 2.2.12 VLOAD * Modification of Table 2-1 Types of Pin I/O Circuits CHAPTER 3 CPU ARCHITECTURE * Addition of Caution in 3.1 Memory Space * Modification of Note in Table 3-3 Special-Function Register List CHAPTER 4 PORT FUNCTIONS * Addition of Caution in 4.2.6 Port 8 * Addition of Caution in 4.2.7 Port 9 * Addition of Caution in 4.2.8 Port 10 * Addition of Caution in 4.2.9 Port 11 * Addition of Caution in 4.2.10 Port 12 CHAPTER 5 CLOCK GENERATOR p.103 * Addition of Note in Figure 5-3 Format of Processor Clock Control Register CHAPTER 6 16-BIT TIMER/EVENT COUNTER * Modification of Caution in Figure 6-8 Format of External Interrupt Mode Register * Modification of 6.6 (5) Valid edge setting CHAPTER 8 WATCH TIMER * Modification of Caution in Figure 8-2 Format of Timer Clock Select Register 2 CHAPTER 9 WATCHDOG TIMER p.178 * Modification of Caution in Figure 9-2 Format of Timer Clock Select Register 2 CHAPTER 11 BUZZER OUTPUT CONTROLLER * Modification of Caution in Figure 11-2 Format of Timer Clock Select Register 2 CHAPTER 16 INTERRUPT AND TEST FUNCTIONS * Addition of Caution in Figure 16-2 Format of Interrupt Request Flag Register * Modification of Caution in Figure 16-5 Format of External Interrupt Mode Register CHAPTER 17 STANDBY FUNCTION * Addition of description in Table 17-1 HALT Mode Operating Status * Addition of description in Table 17-3 STOP Mode Operating Status CHAPTER 19 PD78P0208 * Modification of Table 19-2 Internal Memory Size Switching Register Setting Values APPENDIX A DIFFERENCES BETWEEN PD78044H, 780228, AND 780208 SUBSERIES * Modification of description in Table A-1 Major Differences Between PD78044H, 780228, and 780208 Subseries APPENDIX B DEVELOPMENT TOOLS * Modification of description
p.42 p.43
p.48 p.67
p.90 p.91 p.92 p.93 p.94
p.133 p.144
p.171
p.188
p.340 p.343
p.361 p.364
p.373
p.398
p.399
The mark
shows major revised points.
6
User's Manual U11302EJ4V0UM
INTRODUCTION
Readers
This manual has been prepared for user engineers who wish to understand the functions of the PD780208 Subseries and design and develop its application systems and programs. This manual is intended to give users an understanding of the functions described in the Organization below.
Purpose
Organization
The PD780208 Subseries manual consists of two parts: this manual and Instructions (common to the 78K/0 Series)
PD780208 Subseries User's Manual (This manual)
* Pin functions * Internal block functions * Interrupts * Other on-chip peripheral functions
78K/0 Series Instructions User's Manual * CPU functions * Instruction set * Explanation of each instruction
How to Read This Manual It is assumed that the reader of this manual has general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. * For an understanding of functions in general: Read this manual in the order of the CONTENTS. * For how to interpret the register format: For a bit number enclosed in angle brackets, the bit name is defined as a reserved word in the RA78K0, and is defined in the header file named sfrbit.h in the CC78K0. * To confirm the details of a register whose register name is known: Refer to APPENDIX C REGISTER INDEX. * For the details of PD780208 Subseries instruction functions: Refer to 78K/0 Series Instructions User's Manual (U12326E).
* For the electrical specifications of the PD780208 Subseries:
Refer to the separate PD780204, 780205, 780206, 780208 Data Sheet (U10436E) and
PD78P0208 Data Sheet (U11295E).
* For application examples of the PD780208 Subseries:
Refer to the separate 78K/0 Series Basics (II) Application Note (U10121E). Conventions Data significance: Active low representation: Note: Caution: Remark: Numerical representation: Higher digits on the left and lower digits on the right xxx (overscore over pin or signal name) Footnote for item marked with Note in the text Information requiring particular attention Supplementary information Binary .................. xxxx or xxxxB Decimal ............... xxxx Hexadecimal ....... xxxxH
User's Manual U11302EJ4V0UM
7
Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices
Document Name Document No. U10436E U11295E This manual U12326E U10121E
PD780204, 780205, 780206, 780208 Data Sheet PD78P0208 Data Sheet PD780208 Subseries User's Manual
78K/0 Series Instructions User's Manual 78K/0 Series Basic (II) Application Note
Documents Related to Software Development Tools (User's Manuals)
Document Name RA78K0 Assembler Package Operation Language Structured Assembly Language CC78K0 C Compiler Operation Language SM78K Series System Simulator Ver. 2.30 or Later Operation (Windows
TM
Document No. U14445E U14446E U11789E U14297E U14298E Based) U15373E U15802E U15185E U11537E U11536E U14610E
External Part User Open Interface Specification ID78K Series Integrated Debugger Ver. 2.30 or Later RX78K0 Real-Time OS Operation (Windows Based) Fundamentals Installation Project Manager Ver. 3.12 or Later (Windows Based)
Documents Related to Hardware Development Tools (User's Manuals)
Document Name IE-78K0-NS In-Circuit Emulator IE-78K0-NS-A In-Circuit Emulator IE-780208-NS-EM1 Emulation Board IE-78001-R-A In-Circuit Emulator IE-780208-R-EM Emulation Board Document No. U13731E U14889E U13691E U14142E EEU-1501
Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
8
User's Manual U11302EJ4V0UM
Documents Related to PROM Writing (User's Manuals)
Document Name PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOS IBM PC Series (PC DOS
TM
Document No. U11940E Based) EEU-1291 U10540E
TM
Based)
Other Related Documents
Document Name SEMICONDUCTOR SELECTION GUIDE - Products and Packages Semiconductor Device Mount Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Document No. X13769X Note C11531E C10983E C11892E
Note See the "Semiconductor Device Mount Manual" website (http://www.necel.com/pkg/en/mount/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
User's Manual U11302EJ4V0UM
9
CONTENTS
CHAPTER 1 OUTLINE ......................................................................................................................... 1.1 Features ............................................................................................................................... 1.2 Applications ......................................................................................................................... 1.3 Ordering Information .......................................................................................................... 1.4 Quality Grade ...................................................................................................................... 1.5 Pin Configuration (Top View) ............................................................................................ 1.6 78K/0 Series Lineup ........................................................................................................... 1.7 Block Diagram ..................................................................................................................... 1.8 Overview of Functions ....................................................................................................... 1.9 Mask Options ......................................................................................................................
24 24 25 25 25 26 29 31 32 33
CHAPTER 2 PIN FUNCTIONS .............................................................................................................. 34 2.1 Pin Function List................................................................................................................. 34
2.1.1 2.1.2 Normal operating mode pins .................................................................................................. PROM programming mode pins (PD78P0208 only) ........................................................... P00 to P04 (Port 0) ................................................................................................................. P10 to P17 (Port 1) ................................................................................................................. P20 to P27 (Port 2) ................................................................................................................. P30 to P37 (Port 3) ................................................................................................................. P70 to P74 (Port 7) ................................................................................................................. P80 to P87 (Port 8) ................................................................................................................. P90 to P97 (Port 9) ................................................................................................................. P100 to P107 (Port 10) ........................................................................................................... P110 to P117 (Port 11) ........................................................................................................... 34 37 38 38 39 39 40 40 40 41 41 41 41 42 42 42 42 42 42 42 42 42 42 42
2.2
Description of Pin Functions ............................................................................................ 38
2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 2.2.8 2.2.9
2.2.10 P120 to P127 (Port 12) ........................................................................................................... 2.2.11 FIP0 to FIP12 .......................................................................................................................... 2.2.12 VLOAD ........................................................................................................................................ 2.2.13 AVREF ....................................................................................................................................... 2.2.14 AVDD ......................................................................................................................................... 2.2.15 AVSS ......................................................................................................................................... 2.2.16 RESET ..................................................................................................................................... 2.2.17 X1 and X2 ................................................................................................................................ 2.2.18 XT1 and XT2 ........................................................................................................................... 2.2.19 VDD ........................................................................................................................................... 2.2.20 VSS ............................................................................................................................................ 2.2.21 VPP (PD78P0208 only) .......................................................................................................... 2.2.22 IC (mask ROM version only) ..................................................................................................
2.3
Pin I/O Circuits and Recommended Connection of Unused Pins ............................... 43
CHAPTER 3 CPU ARCHITECTURE .................................................................................................... 48 3.1 Memory Space ..................................................................................................................... 48
3.1.1 3.1.2 3.1.3 Internal program memory space ............................................................................................ Internal data memory space ................................................................................................... Special-function register (SFR) area ...................................................................................... 53 54 54
10
User's Manual U11302EJ4V0UM
3.1.4
Data memory addressing ........................................................................................................ Control registers ...................................................................................................................... General-purpose registers ...................................................................................................... Special-function registers (SFRs) ........................................................................................... Relative addressing ................................................................................................................. Immediate addressing ............................................................................................................. Table indirect addressing ........................................................................................................ Register addressing ................................................................................................................ Implied addressing .................................................................................................................. Register addressing ................................................................................................................ Direct addressing .................................................................................................................... Short direct addressing ........................................................................................................... Special-function register (SFR) addressing ........................................................................... Register indirect addressing ................................................................................................... Based addressing .................................................................................................................... Based indexed addressing ..................................................................................................... Stack addressing .....................................................................................................................
55 60 63 64 68 69 70 71 72 73 74 75 76 77 78 79 79
3.2
Processor Registers ........................................................................................................... 60
3.2.1 3.2.2 3.2.3
3.3
Instruction Address Addressing ...................................................................................... 68
3.3.1 3.3.2 3.3.3 3.3.4
3.4
Operand Address Addressing .......................................................................................... 72
3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 3.4.9
CHAPTER 4 PORT FUNCTIONS ......................................................................................................... 80 4.1 Port Functions ..................................................................................................................... 80 4.2 Port Configuration .............................................................................................................. 83
4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.9 Port 0 ....................................................................................................................................... Port 1 ....................................................................................................................................... Port 2 ....................................................................................................................................... Port 3 ....................................................................................................................................... Port 7 ....................................................................................................................................... Port 8 ....................................................................................................................................... Port 9 ....................................................................................................................................... Port 10 ..................................................................................................................................... Port 11 ..................................................................................................................................... 83 85 86 88 89 90 91 92 93 94
4.2.10 Port 12 .....................................................................................................................................
4.3 4.4
Port Function Control Registers ...................................................................................... 95 Port Function Operations .................................................................................................. 98
4.4.1 4.4.2 4.4.3 Writing to I/O port .................................................................................................................... Reading from I/O port ............................................................................................................. Operations on I/O port ............................................................................................................ 98 98 98
4.5
Selection of Mask Option .................................................................................................. 99 100 100 100 102 109
CHAPTER 5 CLOCK GENERATOR .................................................................................................... 5.1 Clock Generator Functions ............................................................................................... 5.2 Clock Generator Configuration......................................................................................... 5.3 Clock Generator Control Registers .................................................................................. 5.4 System Clock Oscillator ....................................................................................................
5.4.1 5.4.2
Main system clock oscillator ................................................................................................... 109 Subsystem clock oscillator ..................................................................................................... 110
User's Manual U11302EJ4V0UM
11
5.4.3 5.4.4
Divider ...................................................................................................................................... 113 When subsystem clock is not used ........................................................................................ 113 Main system clock operations ................................................................................................ 115 Subsystem clock operations ................................................................................................... 116 Time required for switchover between system clock and CPU clock .................................. 117 System clock and CPU clock switching procedure ............................................................... 118
5.5
Clock Generator Operations ............................................................................................. 114
5.5.1 5.5.2
5.6
Changing System Clock and CPU Clock Settings ......................................................... 117
5.6.1 5.6.2
CHAPTER 6 16-BIT TIMER/EVENT COUNTER ................................................................................... 6.1 Outline of Timers Incorporated in PD780208 Subseries ............................................ 6.2 16-Bit Timer/Event Counter Functions ............................................................................ 6.3 16-Bit Timer/Event Counter Configuration ..................................................................... 6.4 16-Bit Timer/Event Counter Control Registers .............................................................. 6.5 16-Bit Timer/Event Counter Operations ..........................................................................
6.5.1 6.5.2 6.5.3 6.5.4 6.5.5
119 119 120 122 127 135
Interval timer operations ......................................................................................................... 135 PWM output operations .......................................................................................................... 137 Pulse width measurement operations .................................................................................... 138 External event counter operation ........................................................................................... 140 Square-wave output operation ............................................................................................... 142
6.6
16-Bit Timer/Event Counter Operating Precautions ...................................................... 143
CHAPTER 7 8-BIT TIMER/EVENT COUNTER .................................................................................... 145 7.1 8-Bit Timer/Event Counter Functions .............................................................................. 145
7.1.1 7.1.2 8-bit timer/event counter mode ............................................................................................... 145 16-bit timer/event counter mode ............................................................................................ 148
7.2 7.3 7.4
8-Bit Timer/Event Counter Configuration ....................................................................... 150 8-Bit Timer/Event Counter Control Registers................................................................. 153 8-Bit Timer/Event Counter Operations ............................................................................ 158
7.4.1 7.4.2 8-bit timer/event counter mode ............................................................................................... 158 16-bit timer/event counter mode ............................................................................................ 162
7.5
8-Bit Timer/Event Counter Operating Precautions ........................................................ 166 168 168 169 169 173
CHAPTER 8 WATCH TIMER ............................................................................................................... 8.1 Watch Timer Functions ...................................................................................................... 8.2 Watch Timer Configuration ............................................................................................... 8.3 Watch Timer Control Registers ........................................................................................ 8.4 Watch Timer Operations ....................................................................................................
8.4.1 8.4.2
Watch timer operation ............................................................................................................. 173 Interval timer operation ........................................................................................................... 173
CHAPTER 9 WATCHDOG TIMER ....................................................................................................... 9.1 Watchdog Timer Functions ............................................................................................... 9.2 Watchdog Timer Configuration ........................................................................................ 9.3 Watchdog Timer Control Registers ................................................................................. 9.4 Watchdog Timer Operations .............................................................................................
9.4.1 9.4.2
174 174 175 177 180
Watchdog timer operation ....................................................................................................... 180 Interval timer operation ........................................................................................................... 181
12
User's Manual U11302EJ4V0UM
CHAPTER 10 CLOCK OUTPUT CONTROLLER ................................................................................. 10.1 Clock Output Controller Functions .................................................................................. 10.2 Clock Output Controller Configuration ........................................................................... 10.3 Clock Output Function Control Registers ...................................................................... CHAPTER 11 BUZZER OUTPUT CONTROLLER .............................................................................. 11.1 Buzzer Output Controller Functions ................................................................................ 11.2 Buzzer Output Controller Configuration ......................................................................... 11.3 Buzzer Output Function Control Registers .................................................................... CHAPTER 12 12.1 A/D 12.2 A/D 12.3 A/D 12.4 A/D A/D CONVERTER ......................................................................................................... Converter Functions ................................................................................................... Converter Configuration ............................................................................................ Converter Control Registers ..................................................................................... Converter Operations .................................................................................................
182 182 183 183 186 186 186 187 190 190 190 194 197
12.4.1 Basic operations of A/D converter ......................................................................................... 197 12.4.2 Input voltage and conversion results ..................................................................................... 199 12.4.3 A/D converter operating mode ............................................................................................... 200
12.5
A/D Converter Precautions ............................................................................................... 202 205 206 207 211 217
CHAPTER 13 SERIAL INTERFACE CHANNEL 0 ............................................................................... 13.1 Functions of Serial Interface Channel 0 .......................................................................... 13.2 Configuration of Serial Interface Channel 0 ................................................................... 13.3 Control Registers of Serial Interface Channel 0 ............................................................ 13.4 Operations of Serial Interface Channel 0 ........................................................................
13.4.1 Operation stop mode .............................................................................................................. 217 13.4.2 3-wire serial I/O mode operation ............................................................................................ 218 13.4.3 SBI mode operation ................................................................................................................ 223 13.4.4 2-wire serial I/O mode operation ............................................................................................ 249 13.4.5 SCK0/P27 pin output manipulation ........................................................................................ 255
CHAPTER 14 SERIAL INTERFACE CHANNEL 1 ............................................................................... 14.1 Functions of Serial Interface Channel 1 .......................................................................... 14.2 Configuration of Serial Interface Channel 1 ................................................................... 14.3 Control Registers of Serial Interface Channel 1 ............................................................ 14.4 Operations of Serial Interface Channel 1 ........................................................................
256 256 257 260 268
14.4.1 Operation stop mode .............................................................................................................. 268 14.4.2 3-wire serial I/O mode operation ............................................................................................ 269 14.4.3 3-wire serial I/O mode operation with automatic transmit/receive function ......................... 272
CHAPTER 15 VFD CONTROLLER/DRIVER ........................................................................................ 15.1 VFD Controller/Driver Functions ...................................................................................... 15.2 VFD Controller/Driver Configuration ............................................................................... 15.3 VFD Controller/Driver Control Registers ........................................................................
299 299 301 303
15.3.1 Control registers ...................................................................................................................... 303 15.3.2 One-display period and cut width ........................................................................................... 310
15.4 15.5 15.6
Selecting Display Mode ..................................................................................................... 311 Display Mode and Display Output.................................................................................... 312 Display Data Memory ......................................................................................................... 313
User's Manual U11302EJ4V0UM
13
15.7
Key Scan Flag and Key Scan Data .................................................................................. 314
15.7.1 Key scan flag ........................................................................................................................... 314 15.7.2 Key scan data .......................................................................................................................... 314
15.8 15.9
Light Leakage of VFD ......................................................................................................... 315 Display Examples ............................................................................................................... 317
15.9.1 Segment type (display mode 1: DSPM05 = 0) ...................................................................... 318 15.9.2 Dot type (display mode 1: DSPM05 = 0) ............................................................................... 320 15.9.3 Display type in which a segment spans two or more grids (display mode 2: DSPM05 = 1) .............................................................................................. 322
15.10 Calculating Total Power Dissipation............................................................................... 326
15.10.1 Segment type (display mode 1: DSPM05 = 0) ...................................................................... 326 15.10.2 Dot type (display mode 1: DSPM05 = 0) ............................................................................... 329 15.10.3 Display type in which a segment spans two or more grids (display mode 2: DSPM05 = 1) .............................................................................................. 332
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS .......................................................................... 16.1 Interrupt Function Types ................................................................................................... 16.2 Interrupt Sources and Configuration ............................................................................... 16.3 Interrupt Function Control Registers .............................................................................. 16.4 Interrupt Servicing Operations .........................................................................................
335 335 336 339 347
16.4.1 Non-maskable interrupt request acknowledgment operation ................................................ 347 16.4.2 Maskable interrupt request acknowledgment operation ........................................................ 350 16.4.3 Software interrupt request acknowledgment operation ......................................................... 352 16.4.4 Multiple interrupt servicing ...................................................................................................... 353 16.4.5 Interrupt request hold .............................................................................................................. 356
16.5
Test Functions .................................................................................................................... 357
16.5.1 Test function control registers ................................................................................................ 357 16.5.2 Test input signal acknowledgment operation ........................................................................ 358
CHAPTER 17 STANDBY FUNCTION ................................................................................................... 359 17.1 Standby Function and Configuration .............................................................................. 359
17.1.1 Standby function ...................................................................................................................... 359 17.1.2 Standby function control register ............................................................................................ 360
17.2
Standby Function Operations ........................................................................................... 361
17.2.1 HALT mode ............................................................................................................................. 361 17.2.2 STOP mode ............................................................................................................................. 364
CHAPTER 18 RESET FUNCTION ........................................................................................................ 367 18.1 Reset Function .................................................................................................................... 367 CHAPTER 19 PD78P0208 .................................................................................................................. 19.1 Internal Memory Size Switching Register ....................................................................... 19.2 Internal Expansion RAM Size Switching Register ......................................................... 19.3 PROM Programming ........................................................................................................... 371 372 374 375
19.3.1 Operating modes ..................................................................................................................... 375 19.3.2 PROM write procedure ........................................................................................................... 377 19.3.3 PROM read procedure ............................................................................................................ 381
19.4
Screening of One-Time PROM Version ........................................................................... 382
14
User's Manual U11302EJ4V0UM
CHAPTER 20 INSTRUCTION SET ....................................................................................................... 383 20.1 Conventions ........................................................................................................................ 384
20.1.1 Operand identifiers and description methods ........................................................................ 384 20.1.2 Description of "operation" column .......................................................................................... 385 20.1.3 Description of "flag operation" column ................................................................................... 385
20.2 20.3
Operation List ...................................................................................................................... 386 Instructions Listed by Addressing Type ......................................................................... 394
APPENDIX A DIFFERENCES BETWEEN PD78044H, 780228, AND 780208 SUBSERIES ............ 398 APPENDIX B DEVELOPMENT TOOLS .............................................................................................. B.1 Software Package ............................................................................................................... B.2 Language Processing Software ........................................................................................ B.3 Control Software ................................................................................................................. B.4 PROM Programming Tools ................................................................................................
B.4.1 B.4.2
399 401 401 402 403
Hardware ................................................................................................................................. 403 Software ................................................................................................................................... 403 When using in-circuit emulator IE-78K0-NS, IE-78K0-NS-A ................................................ 404 When using in-circuit emulator IE-78001-R-A ....................................................................... 405
B.5
Debugging Tools (Hardware) ............................................................................................ 404
B.5.1 B.5.2
Debugging Tools (Software) ............................................................................................. Embedded Software ........................................................................................................... Method for Upgrading from Former In-Circuit Emulator for 78K/0 Series to IE-78001-R-A ........................................................................................................................ B.9 Conversion Socket (EV-9200GF-100) Package Drawing and Recommended Footprint ............................................................................................................................... B.10 Notes on Target System Design .......................................................................................
B.6 B.7 B.8
406 407 408 409 411
APPENDIX C REGISTER INDEX ......................................................................................................... 413 C.1 Register Index (by Register Name) .................................................................................. 413 C.2 Register Index (by Register Symbol) ............................................................................... 415 APPENDIX D REVISION HISTORY ....................................................................................................... 417
User's Manual U11302EJ4V0UM
15
LIST OF FIGURES (1/6)
Figure No. 2-1 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10
Title Pin I/O Circuits ................................................................................................................................ Memory Map (PD780204 and PD780204A) .............................................................................. Memory Map (PD780205 and PD780205A) .............................................................................. Memory Map (PD780206) ............................................................................................................. Memory Map (PD780208) ............................................................................................................. Memory Map (PD78P0208) .......................................................................................................... Data Memory Addressing (PD780204 and PD780204A) .......................................................... Data Memory Addressing (PD780205 and PD780205A) .......................................................... Data Memory Addressing (PD780206) ........................................................................................ Data Memory Addressing (PD780208) ........................................................................................ Data Memory Addressing (PD78P0208) ...................................................................................... Program Counter Format ................................................................................................................ Program Status Word Format ......................................................................................................... Stack Pointer Format ...................................................................................................................... Data to Be Saved to Stack Memory ............................................................................................... Data to Be Reset from Stack Memory ........................................................................................... General-Purpose Register Configuration ....................................................................................... Port Types ....................................................................................................................................... Block Diagram of P00 and P04 ...................................................................................................... Block Diagram of P01 to P03 ......................................................................................................... Block Diagram of P10 to P17 ......................................................................................................... Block Diagram of P20, P21, P23 to P26 ........................................................................................ Block Diagram of P22 and P27 ...................................................................................................... Block Diagram of P30 to P37 ......................................................................................................... Block Diagram of P70 to P74 ......................................................................................................... Block Diagram of P80 to P87 ......................................................................................................... Block Diagram of P90 to P97 ......................................................................................................... Block Diagram of P100 to P107 ..................................................................................................... Block Diagram of P110 to P117 ..................................................................................................... Block Diagram of P120 to P127 ..................................................................................................... Format of Port Mode Register ........................................................................................................ Format of Pull-up Resistor Option Register ...................................................................................
Page 45 48 49 50 51 52 55 56 57 58 59 60 60 61 62 62 63 80 84 84 85 86 87 88 89 90 91 92 93 94 96 97
Clock Generater Block Diagram ..................................................................................................... 101 Feedback Resistor of Subsystem Clock ........................................................................................ 102 Format of Processor Clock Control Register ................................................................................. 103 Format of Display Mode Register 0 ............................................................................................... 105 Format of Display Mode Register 1 ............................................................................................... 108 External Circuit of Main System Clock Oscillator .......................................................................... 109 External Circuit of Subsystem Clock Oscillator ............................................................................. 110 Examples of Incorrect Resonator Connection ............................................................................... 111 Main System Clock Stop Function ................................................................................................. 115 System Clock and CPU Clock Switching ....................................................................................... 118
User's Manual U11302EJ4V0UM
16
LIST OF FIGURES (2/6)
Figure No. 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 6-17 6-18 6-19 6-20 6-21 6-22 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16
Title
Page
Block Diagram of 16-Bit Timer/Event Counter (Timer Mode) ....................................................... 123 Block Diagram of 16-Bit Timer/Event Counter (PWM Mode) ........................................................ 124 Block Diagram of 16-Bit Timer/Event Counter Output Controller ................................................. 125 Format of Timer Clock Select Register 0 ....................................................................................... 128 Format of 16-Bit Timer Mode Control Register ............................................................................. 130 Format of 16-Bit Timer Output Control Register ........................................................................... 131 Format of Port Mode Register 3 ..................................................................................................... 132 Format of External Interrupt Mode Register .................................................................................. 133 Format of Sampling Clock Select Register .................................................................................... 134 Interval Timer Configuration Diagram ............................................................................................ 135 Interval Timer Operation Timing ..................................................................................................... 136 Example of D/A Converter Configuration with PWM Output ......................................................... 137 TV Tuner Application Circuit Example ........................................................................................... 138 Configuration Diagram for Pulse Width Measurement in Free-Running Mode ............................ 139 Timing of Pulse Width Measurement Operation in Free-Running Mode (with Both Edges Specified) ........................................................................................................... 139 Timing of Pulse Width Measurement Operation by Means of Restart (with Both Edges Specified) ........................................................................................................... 140 External Event Counter Configuration Diagram ............................................................................ 141 External Event Counter Operation Timing (with Rising Edge Specified) ..................................... 141 Square-Wave Output Operation Timing ......................................................................................... 142 16-Bit Timer Register Start Timing ................................................................................................. 143 Timing After Compare Register Change During Timer Count Operation ..................................... 143 Capture Register Data Retention Timing ....................................................................................... 144 Block Diagram of 8-Bit Timer/Event Counter ................................................................................. 151 Block Diagram of 8-Bit Timer/Event Counter Output Controller 1 ................................................ 152 Block Diagram of 8-Bit Timer/Event Counter Output Controller 2 ................................................ 152 Format of Timer Clock Select Register 1 ....................................................................................... 154 Format of 8-Bit Timer Mode Control Register ............................................................................... 155 Format of 8-Bit Timer Output Control Register .............................................................................. 156 Format of Port Mode Register 3 ..................................................................................................... 157 Interval Timer Operation Timing ..................................................................................................... 158 External Event Counter Operation Timing (with Rising Edge Specified) ..................................... 160 Square-Wave Output Operation Timing ......................................................................................... 161 Interval Timer Operation Timing ..................................................................................................... 162 External Event Counter Operation Timing (with Rising Edge Specified) ..................................... 164 Square-Wave Output Operation Timing ......................................................................................... 165 8-Bit Timer Register Start Timing ................................................................................................... 166 External Event Counter Operation Timing ..................................................................................... 166 Timing After Compare Register Change During Timer Count Operation ..................................... 167
User's Manual U11302EJ4V0UM
17
LIST OF FIGURES (3/6)
Figure No. 8-1 8-2 8-3 9-1 9-2 9-3 10-1 10-2 10-3 10-4 11-1 11-2 11-3 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 13-12 13-13 13-14 13-15
Title
Page
Watch Timer Block Diagram ........................................................................................................... 170 Format of Timer Clock Select Register 2 ....................................................................................... 171 Format of Watch Timer Mode Control Register ............................................................................. 172 Watchdog Timer Block Diagram ..................................................................................................... 176 Format of Timer Clock Select Register 2 ....................................................................................... 178 Format of Watchdog Timer Mode Register .................................................................................... 179 Remote Controlled Output Application Example ........................................................................... 182 Clock Output Controller Block Diagram ......................................................................................... 183 Format of Timer Clock Select Register 0 ....................................................................................... 184 Format of Port Mode Register 3 ..................................................................................................... 185 Buzzer Output Controller Block Diagram ....................................................................................... 186 Format of Timer Clock Select Register 2 ....................................................................................... 188 Format of Port Mode Register 3 ..................................................................................................... 189 A/D Converter Block Diagram ........................................................................................................ 191 Format of A/D Converter Mode Register ....................................................................................... 195 Format of A/D Converter Input Select Register ............................................................................. 196 Basic Operation of A/D Converter .................................................................................................. 198 Relationship Between Analog Input Voltage and A/D Conversion Result ................................... 199 A/D Conversion by Hardware Start ................................................................................................ 200 A/D Conversion by Software Start ................................................................................................. 201 Example of Method of Reducing Power Consumption in Standby Mode .................................... 202 Analog Input Pin Processing .......................................................................................................... 203 A/D Conversion End Interrupt Request Generation Timing .......................................................... 204 AVDD Pin Connection ....................................................................................................................... 204 Block Diagram of Serial Interface Channel 0 ................................................................................ 208 Format of Timer Clock Select Register 3 ....................................................................................... 212 Format of Serial Operating Mode Register 0 ................................................................................. 213 Format of Serial Bus Interface Control Register ........................................................................... 214 Format of Interrupt Timing Specification Register ......................................................................... 216 3-Wire Serial I/O Mode Timing ....................................................................................................... 221 RELT and CMDT Operations .......................................................................................................... 222 Circuit for Switching Transfer Bit Order ......................................................................................... 222 Example of Serial Bus Configuration with SBI .............................................................................. 224 SBI Transfer Timing ........................................................................................................................ 226 Bus Release Signal ......................................................................................................................... 227 Command Signal ............................................................................................................................. 227 Address ............................................................................................................................................ 228 Slave Selection by Address ............................................................................................................ 228 Commands ....................................................................................................................................... 229
18
User's Manual U11302EJ4V0UM
LIST OF FIGURES (4/6)
Figure No. 13-16 13-17 13-18 13-19 13-20 13-21 13-22 13-23 13-24 13-25 13-26 13-27 13-28 13-29 13-30 13-31 13-32 13-33 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 14-13 14-14 14-15 14-16 14-17 14-18 14-19 14-20 14-21 14-22 14-23 14-24
Title
Page
Data .................................................................................................................................................. 229 Acknowledge Signal ........................................................................................................................ 230 BUSY and READY Signals ............................................................................................................. 231 RELT, CMDT, RELD, and CMDD Operations (Master) ................................................................ 236 RELD and CMDD Operations (Slave) ............................................................................................ 236 ACKT Operation .............................................................................................................................. 237 ACKE Operations ............................................................................................................................ 238 ACKD Operations ............................................................................................................................ 239 BSYE Operation .............................................................................................................................. 239 Pin Configuration ............................................................................................................................. 242 Address Transmission from Master Device to Slave Device (WUP = 1) ..................................... 244 Command Transmission from Master Device to Slave Device .................................................... 245 Data Transmission from Master Device to Slave Device .............................................................. 246 Data Transmission from Slave Device to Master Device .............................................................. 247 Serial Bus Configuration Example Using 2-Wire Serial I/O Mode ................................................ 249 2-Wire Serial I/O Mode Timing ....................................................................................................... 253 RELT and CMDT Operations .......................................................................................................... 254 SCK0/P27 Pin Configuration .......................................................................................................... 255 Block Diagram of Serial Interface Channel 1 ................................................................................ 258 Format of Timer Clock Select Register 3 ....................................................................................... 261 Format of Serial Operating Mode Register 1 ................................................................................. 262 Format of Automatic Data Transmit/Receive Control Register ..................................................... 264 Format of Automatic Data Transmit/Receive Interval Specification Register .............................. 265 3-Wire Serial I/O Mode Timing ....................................................................................................... 270 Circuit for Switching Transfer Bit Order ......................................................................................... 271 Basic Transmission/Reception Mode Operation Timing ............................................................... 279 Basic Transmission/Reception Mode Flowchart ............................................................................ 280 Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmission/Reception Mode) ....................................................................................... 281 Basic Transmission Mode Operation Timing ................................................................................. 283 Basic Transmission Mode Flowchart .............................................................................................. 284 Buffer RAM Operation in 6-Byte Transmission (in Basic Transmission Mode) ........................... 285 Repeat Transmission Mode Operation Timing .............................................................................. 287 Repeat Transmission Mode Flowchart ........................................................................................... 288 Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmission Mode) ........................ 289 Automatic Transmission/Reception Suspension and Restart ....................................................... 291 System Configuration with Busy Control Option ........................................................................... 292 Operation Timing When Using Busy Control Option (BUSY0 = 0) .............................................. 293 Busy Signal and Clearing Wait (BUSY0 = 0) ................................................................................ 293 Operation Timing When Using Busy & Strobe Control Option (BUSY0 = 0) ............................... 294 Operation Timing of Bit Slippage Detection Function Using Busy Signal (BUSY0 = 1) ............. 295 Automatic Transmit/Receive Interval .............................................................................................. 296 Operation Timing When Automatic Transmit/Receive Function Is Operating with Internal Clock ................................................................................................................................... 297
User's Manual U11302EJ4V0UM
19
LIST OF FIGURES (5/6)
Figure No. 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 15-10 15-11 15-12 15-13 15-14 15-15 15-16 15-17 15-18 15-19 15-20 15-21 15-22 15-23 15-24 15-25 15-26 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 16-11
Title
Page
VFD Controller Operation Timing in Display Mode 1 (DSPM05 = 0) ........................................... 300 VFD Controller/Driver Block Diagram ............................................................................................ 302 Format of Display Mode Register 0 ............................................................................................... 305 Format of Display Mode Register 1 ............................................................................................... 307 Format of Display Mode Register 2 ............................................................................................... 308 Cut Width of Segment/Digit Signal ................................................................................................. 310 VFD Controller Display Start Timing .............................................................................................. 310 Selection of Display Mode .............................................................................................................. 311 Pin Configuration for 14-Segment Display ..................................................................................... 312 Relationship Between Display Data Memory Contents and Segment Output ............................. 313 Light Leakage due to Short Blanking Time .................................................................................... 315 Light Leakage due to CSG ............................................................................................................... 316 Waveform of Light Leakage due to CSG ......................................................................................... 316 Display Data Memory Configuration and Segment Data Reading Order (Segment Type) ............................................................................................................................... 318 Relationship Between Display Data Memory Contents and Segment Outputs in 10-Segment x 11-Digit Display Mode ........................................................................................ 319 Display Data Memory Configuration and Segment Data Reading Order (Dot Type) .................. 320 Relationship Between Display Data Memory Contents and Segment Outputs in 35-Segment x 16-Digit Display Mode ........................................................................................ 321 Display Data Memory Configuration and Data Reading Order (Display Mode 2) ....................... 322 Segment Connection Example ....................................................................................................... 323 Grid Driving Timing ......................................................................................................................... 324 Data Memory Status in 23-Segment x 5-Grid Display Mode ........................................................ 325 Allowable Total Power Dissipation PT (TA = -40 to +85C) .......................................................... 326 Relationship Between Display Data Memory Contents and Segment Outputs in 10-Segment x 11-Digit Display Mode ........................................................................................ 328 Relationship Between Display Data Memory Contents and Segment Outputs in 35-Segment x 16-Digit Display Mode ........................................................................................ 331 Grid Driving Timing ......................................................................................................................... 333 Data Memory Status in 23-Segment x 5-Grid Display Mode ........................................................ 334 Basic Configuration of Interrupt Function ...................................................................................... 337 Format of Interrupt Request Flag Register .................................................................................... 340 Format of Interrupt Mask Flag Register ......................................................................................... 341 Format of Priority Specification Flag Register ............................................................................... 342 Format of External Interrupt Mode Register .................................................................................. 343 Format of Sampling Clock Select Register .................................................................................... 344 Noise Eliminator I/O Timing (When Rising Edge Is Detected) ..................................................... 345 Format of Program Status Word .................................................................................................... 346 Non-Maskable Interrupt Request Acknowledgment Flowchart ..................................................... 348 Non-Maskable Interrupt Request Acknowledgment Timing .......................................................... 348 Non-Maskable Interrupt Request Acknowledgment Operation ..................................................... 349
20
User's Manual U11302EJ4V0UM
LIST OF FIGURES (6/6)
Figure No. 16-12 16-13 16-14 16-15 16-16 16-17 16-18 16-19 17-1 17-2 17-3 17-4 17-5 18-1 18-2 18-3 18-4 19-1 19-2 19-3 19-4 19-5 19-6 19-7 B-1 B-2 B-3 B-4 B-5 B-6
Title
Page
Interrupt Request Acknowledge Processing Algorithm ................................................................. 351 Interrupt Request Acknowledgment Timing (Minimum Time) ....................................................... 352 Interrupt Request Acknowledgment Timing (Maximum Time) ...................................................... 352 Multiple Interrupt Servicing Example .............................................................................................. 354 Interrupt Request Hold .................................................................................................................... 356 Basic Configuration of Test Function ............................................................................................. 357 Format of Interrupt Request Flag Register 0H .............................................................................. 358 Format of Interrupt Mask Flag Register 0H ................................................................................... 358 Format of Oscillation Stabilization Time Select Register .............................................................. 360 HALT Mode Release by Interrupt Request Generation ................................................................ 362 HALT Mode Release by RESET Input ........................................................................................... 363 STOP Mode Release by Interrupt Request Generation ................................................................ 365 STOP Mode Release by RESET Input .......................................................................................... 366 Block Diagram of Reset Function ................................................................................................... 367 Timing of Reset by RESET Input ................................................................................................... 368 Timing of Reset due to Watchdog Timer Overflow ....................................................................... 368 Timing of Reset by RESET Input in STOP Mode .......................................................................... 368 Format of Internal Memory Size Switching Register (IMS) ........................................................... 373 Format of Internal Expansion RAM Size Switching Register ........................................................ 374 Page Program Mode Flowchart ...................................................................................................... 377 Page Program Mode Timing ........................................................................................................... 378 Byte Program Mode Flowchart ....................................................................................................... 379 Byte Program Mode Timing ............................................................................................................ 380 PROM Read Timing ........................................................................................................................ 381 Configuration of Development Tools .............................................................................................. 400 EV-9200GF-100 Package Drawing (for Reference Purposes only) ............................................. 409 Recommended Footprint for EV-9200GF-100 (for Reference Purposes only) ............................ 410 Distance Between IE System and Conversion Adapter ................................................................ 411 Connection Conditions of Target System (When NP-100GF-TQ Is Used) .................................. 412 Connection Conditions of Target System (When NP-H100GF-TQ Is Used) ............................... 412
User's Manual U11302EJ4V0UM
21
LIST OF TABLES (1/2)
Table No. 1-1 2-1 3-1 3-2 3-3 4-1 4-2 4-3 4-4 5-1 5-2 5-3 6-1 6-2 6-3 6-4 6-5 6-6 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10
Title Mask Options in Mask ROM Versions ........................................................................................... Types of Pin I/O Circuits ................................................................................................................. Internal ROM Capacity .................................................................................................................... Vector Table .................................................................................................................................... Special-Function Register List ........................................................................................................ Port Functions ................................................................................................................................. Port Configuration ........................................................................................................................... Port Mode Register and Output Latch Setting When Alternate Function Is Used ...................... Comparison Between Mask Option of Mask ROM Version and PD78P0208 ............................
Page 33 43 53 53 65 81 83 95 99
Clock Generator Configuration ....................................................................................................... 100 Relationship Between CPU Clock and Minimum Instruction Execution Time ............................. 104 Maximum Time Required for CPU Clock Switchover .................................................................... 117 Timer/Event Counter Operations .................................................................................................... 120 16-Bit Timer/Event Counter Interval Time ..................................................................................... 121 16-Bit Timer/Event Counter Square-Wave Output Ranges .......................................................... 121 16-Bit Timer/Event Counter Configuration ..................................................................................... 122 16-Bit Timer/Event Counter Interval Time ..................................................................................... 136 16-Bit Timer/Event Counter Square-Wave Output Ranges .......................................................... 142 8-Bit Timer/Event Counter Interval Time ........................................................................................ 146 8-Bit Timer/Event Counter Square-Wave Output Ranges ............................................................ 147 Interval Time When 8-Bit Timer/Event Counter Is Used as 16-Bit Timer/Event Counter ........... 148 Square-Wave Output Ranges When 8-Bit Timer/Event Counter Is Used as 16-Bit Timer/Event Counter ......................................................................................... 149 8-Bit Timer/Event Counter Configuration ....................................................................................... 150 8-Bit Timer/Event Counter 1 Interval Time .................................................................................... 159 8-Bit Timer/Event Counter 2 Interval Time .................................................................................... 159 8-Bit Timer/Event Counter Square-Wave Output Ranges ............................................................ 161 Interval Time When 2-Channel 8-Bit Timer/Event Counter (TM1 and TM2) Is Used as 16-Bit Timer/Event Counter .............................................................. 163 Square-Wave Output Ranges When 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) Are Used as 16-Bit Timer/Event Counter ........................................................... 165
8-1 8-2 8-3 9-1 9-2 9-3 9-4
Interval Timer Interval Time ............................................................................................................ 168 Watch Timer Configuration ............................................................................................................. 169 Interval Timer Interval Time ............................................................................................................ 173 Watchdog Timer Program Loop Detection Time ........................................................................... 174 Interval Time .................................................................................................................................... 174 Watchdog Timer Configuration ....................................................................................................... 175 Watchdog Timer Program Loop Detection Time ........................................................................... 180
22
User's Manual U11302EJ4V0UM
LIST OF TABLES (2/2)
Table No. 9-5 10-1 11-1 12-1 13-1 13-2 13-3 13-4 14-1 14-2 14-3 14-4 15-1 15-2 15-3 16-1 16-2 16-3 16-4 17-1 17-2 17-3 17-4 18-1 19-1 19-2 19-3 19-4 20-1 A-1 B-1 B-2
Title
Page
Interval Timer Interval Time ............................................................................................................ 181 Clock Output Controller Configuration ........................................................................................... 183 Buzzer Output Controller Configuration ......................................................................................... 186 A/D Converter Configuration ........................................................................................................... 190 Differences Between Channels 0 and 1 ......................................................................................... 205 Modes of Serial Interface Channel 0 .............................................................................................. 206 Configuration of Serial Interface Channel 0 ................................................................................... 207 Signals in SBI Mode ........................................................................................................................ 240 Modes of Serial Interface Channel 1 .............................................................................................. 256 Configuration of Serial Interface Channel 1 ................................................................................... 257 Interval Determined by CPU Processing (with Internal Clock Operation) .................................... 297 Interval Determined by CPU Processing (with External Clock Operation) .................................. 298 Relationship Between Display Output Pins and Port Pins ............................................................ 301 VFD Controller/Driver Configuration ............................................................................................... 301 Segment Lighting Timing ................................................................................................................ 324 Interrupt Source List ........................................................................................................................ 336 Various Flags Corresponding to Interrupt Request Sources ........................................................ 339 Times from Maskable Interrupt Request Generation to Interrupt Servicing................................. 350 Interrupt Request Enabled for Multiple Interrupt During Interrupt Servicing ................................ 353 HALT Mode Operating Status ......................................................................................................... 361 Operation After HALT Mode Release ............................................................................................ 363 STOP Mode Operating Status ........................................................................................................ 364 Operation After STOP Mode Release ............................................................................................ 366 Hardware Status After Reset .......................................................................................................... 369 Differences Between PD78P0208 and Mask ROM Versions ..................................................... 371 Internal Memory Size Switching Register Setting Values ............................................................. 373 Internal Expansion RAM Size Switching Register Setting Values ................................................ 374 PROM Programming Operating Modes ......................................................................................... 375 Operand Identifiers and Description Methods ............................................................................... 384 Major Differences Between PD78044H, 780228, and 780208 Subseries ................................. 398 Method for Upgrading from Former In-Circuit Emulator for 78K/0 Series to IE-78001-R-A ....... 408 Distance Between IE System and Conversion Adapter ................................................................ 411
User's Manual U11302EJ4V0UM
23
CHAPTER 1
OUTLINE
1.1 Features
Internal high-capacity ROM and RAM
Item Part Number Program Memory ROM PROM Internal HighSpeed RAM 1024 bytes Data Memory Buffer RAM VFD Display RAM 80 bytes Internal Expansion RAM None
PD780204 PD780204A PD780205 PD780205A PD780206 PD780208 PD78P0208
32 KB
--
64 bytes
40 KB
--
48 KB 60 KB -- 60
-- -- KB Note 1
1024 bytes
1024 bytesNote 2
Notes 1. 32, 40, 48, or 60 KB can be selected by setting the internal memory size switching register (IMS). 2. 0 or 1024 bytes can be selected by setting the internal expansion RAM size switching register (IXS). Minimum instruction execution time can be changed from high speed (0.4 s: @ 5.0 MHz operation with main system clock) to ultra-low speed (122 s: @ 32.768 kHz operation with subsystem clock) 74 I/O ports VFD controller/driver: 53 display outputs in total * Segments: 9 to 40 * Digits: 2 to 16 8-bit resolution A/D converter: 8 channels * Power supply voltage (AVDD = 4.0 to 5.5 V) Serial interface: 2 channels * 3-wire serial I/O/SBI/2-wire serial I/O mode: 1 channel * 3-wire serial I/O mode (automatic transmit/receive function): 1 channel Timer: 5 channels * 16-bit timer/event counter: 1 channel * 8-bit timer/event counter: 2 channels * Watch timer: 1 channel * Watchdog timer: 1 channel 15 vectored interrupt sources One test input Two types of on-chip clock oscillators (for main and subsystem clocks) Power supply voltage: VDD = 2.7 to 5.5 V
24
User's Manual U11302EJ4V0UM
CHAPTER 1
OUTLINE
1.2 Applications
Compact home stereo sets, cassette decks, tuners, CD players, VCRs, etc.
1.3 Ordering Information
Part Number Package 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) Internal ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM One-time PROM
PD780204GF-xxx-3BA PD780204AGF-xxx-3BA PD780205GF-xxx-3BA PD780205AGF-xxx-3BA PD780206GF-xxx-3BA PD780208GF-xxx-3BA PD78P0208GF-3BA
Remark xxx indicates ROM code suffix.
1.4 Quality Grade
Part Number Package 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) Quality Grade Standard Standard Standard Standard Standard Standard Standard
PD780204GF-xxx-3BA PD780204AGF-xxx-3BA PD780205GF-xxx-3BA PD780205AGF-xxx-3BA PD780206GF-xxx-3BA PD780208GF-xxx-3BA PD78P0208GF-3BA
Remark xxx indicates ROM code suffix.
User's Manual U11302EJ4V0UM
25
CHAPTER 1
OUTLINE
1.5 Pin Configuration (Top View)
(1) Normal operating mode * 100-pin plastic QFP (14 x 20)
PD780204GF-xxx-3BA, 780204AGF-xxx-3BA, 780205GF-xxx-3BA, 780205AGF-xxx-3BA, PD780206GF-xxx-3BA, 780208GF-xxx-3BA, 78P0208GF-3BA
FIP0 FIP1 FIP2 FIP3 FIP4 FIP5 FIP6 FIP7 FIP8 FIP9 FIP10 FIP11 FIP12 P80/FIP13 P81/FIP14 P82/FIP15 P83/FIP16 P84/FIP17 P85/FIP18 P86/FIP19
VDD P37 P36/BUZ P35/PCL P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 RESET X2 X1 IC (VPP) XT2 P04/XT1 VDD P27/SCK0 P26/SO0/SB1 P25/SI0/SB0 P24/BUSY P23/STB P22/SCK1 P21/SO1 P20/SI1 AVSS P17/ANI7 P16/ANI6 P15/ANI5 P14/ANI4 P13/ANI3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P87/FIP20 VLOAD P90/FIP21 P91/FIP22 P92/FIP23 P93/FIP24 P94/FIP25 P95/FIP26 P96/FIP27 P97/FIP28 P100/FIP29 P101/FIP30 P102/FIP31 P103/FIP32 P104/FIP33 P105/FIP34 P106/FIP35 P107/FIP36 P110/FIP37 P111/FIP38 P112/FIP39 P113/FIP40 P114/FIP41 P115/FIP42 P116/FIP43 P117/FIP44 P120/FIP45 P121/FIP46 P122/FIP47 P123/FIP48
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS. 2. Connect the AVDD pin to VDD. 3. Connect the AVSS pin to VSS. Remark The pin connection in parentheses is intended for the PD78P0208.
26
P12/ANI2 P11/ANI1 P10/ANI0 AVDD AVREF P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0/TI0 VSS P74 P73 P72 P71 P70 VDD P127/FIP52 P126/FIP51 P125/FIP50 P124/FIP49
User's Manual U11302EJ4V0UM
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CHAPTER 1
OUTLINE
ANI0 to ANI7: AVDD: AVREF: AVSS: BUSY: BUZ: FIP0 to FIP52: IC: INTP0 to INTP3: P00 to P04: P10 to P17: P20 to P27: P30 to P37: P70 to P74: P80 to P87: P90 to P97: P100 to P107:
Analog input Analog power supply Analog reference voltage Analog ground Busy Buzzer clock Fluorescent indicator panel Internally connected External interrupt input Port 0 Port 1 Port 2 Port 3 Port 7 Port 8 Port 9 Port 10
P110 to P117: P120 to P127: PCL: RESET: SB0, SB1: SCK0, SCK1: SI0, SI1: SO0, SO1: STB: TI0 to TI2: TO0 to TO2: VDD: VLOAD: VPP: VSS: X1, X2: XT1, XT2:
Port 11 Port 12 Programmable clock Reset Serial bus Serial clock Serial input Serial output Strobe Timer input Timer output Power supply Negative power supply Programming power supply Ground Crystal (main system clock) Crystal (subsystem clock)
User's Manual U11302EJ4V0UM
27
CHAPTER 1
OUTLINE
(2) PROM programming mode * 100-pin plastic QFP (14 x 20)
PD78P0208GF-3BA
(L)
VDD D7 D6 D5 (D) D4 D3 D2 D1 D0 RESET Open (L) VPP Open (L) VDD A7 A6 A5 (D) A4 A3 A2 A1 A0 VSS (L) (D) CE OE (L)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
VDD VSS (L) (D) PGM (L) A9 VSS
(L)
VDD
Cautions 1. (L): 2. (D): 3. VSS: 5. Open: A0 to A16: Address bus CE: Chip enable D0 to D7: Data bus
Connect independently to VSS via a pull-down resistor. Connect via a driver. Connect to ground. Do not connect to anything. OE: PGM: Output enable Program VDD: Power supply VPP: Programming power supply VSS: Ground
4. RESET: Set to low level.
RESET: Reset
28
(L)
User's Manual U11302EJ4V0UM
(L)
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
(L) VSS
(L)
A8 A16 A10 A11 A12 A13 A14 A15 (L)
(D)
CHAPTER 1
OUTLINE
1.6 78K/0 Series Lineup
The 78K/0 Series product lineup is illustrated below. The part numbers in boxes indicate subseries names.
Products in mass production
Products under development
Y subseries products are compatible with I2C bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 52-pin 52-pin 64-pin 64-pin 42/44-pin
PD78075B PD78078 PD78070A PD780058 PD78058F PD78054 PD780065 PD780078 PD780034A PD780024A PD780034AS
PD780024AS PD78014H PD78018F PD78083
Inverter control
EMI-noise reduced version of the PD78078
PD78078Y PD78070AY PD780018AY PD780058Y PD78058FY PD78054Y
PD78054 with timer and enhanced external interface
ROMless version of the PD78078 PD78078Y with enhanced serial I/O and limited functions
PD78054 with enhanced serial I/O
EMI-noise reduced version of the PD78054
PD78018F with UART and D/A converter, and enhanced I/O PD780024A with expanded RAM PD780034A with timer and enhanced serial I/O PD780078Y PD780034AY PD780024A with enhanced A/D converter PD780024AY PD78018F with enhanced serial I/O 52-pin version of the PD780034A
52-pin version of the PD780024A EMI-noise reduced version of the PD78018F
PD78018FY
Basic subseries for control On-chip UART, capable of operating at low voltage (1.8 V)
64-pin
PD780988
VFD drive
On-chip inverter controller and UART. EMI-noise reduced.
100-pin 80-pin 80-pin 80-pin
PD780208 PD780232 PD78044H PD78044F
LCD drive
PD78044F with enhanced I/O and VFD C/D. Display output total: 53
For panel control. On-chip VFD C/D. Display output total: 53
PD78044F with N-ch open-drain I/O. Display output total: 34
Basic subseries for driving VFD. Display output total: 34
78K/0 Series
100-pin 100-pin 120-pin 120-pin 120-pin 100-pin 100-pin 100-pin
PD780354 PD780344 PD780338 PD780328 PD780318 PD780308 PD78064B PD78064
PD780354Y PD780344Y
PD780344 with enhanced A/D converter PD780308 with enhanced display function and timer. PD780308 with enhanced display function and timer. PD780308 with enhanced display function and timer. PD780308 with enhanced display function and timer.
Segment signal output: 40 pins max. Segment signal output: 40 pins max. Segment signal output: 32 pins max. Segment signal output: 24 pins max.
PD780308Y PD78064Y
PD78064 with enhanced SIO, and expanded ROM and RAM EMI-noise reduced version of the PD78064
Basic subseries for driving LCDs, on-chip UART
Bus interface supported 100-pin 80-pin 80-pin 80-pin 80-pin 64-pin
PD780948 PD78098B PD780702Y PD780703AY PD780833Y
PD780816
Meter control
On-chip CAN controller
PD78054 with IEBusTM controller
On-chip IEBus controller On-chip CAN controller On-chip controller compliant with J1850 (Class 2) Specialized for CAN controller function
100-pin 80-pin 80-pin
PD780958 PD780852 PD780828B
For industrial meter control On-chip automobile meter controller/driver For automobile meter driver. On-chip CAN controller
Remark
VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some documents, but the functions of the two are the same.
User's Manual U11302EJ4V0UM
29
CHAPTER 1
OUTLINE
The following lists the main functional differences between subseries products. * Non-Y subseries
Function Subseries Name Control ROM Timer 8-Bit 10-Bit 8-Bit Capacity (Bytes) 8-Bit 16-Bit Watch WDT A/D A/D D/A 1 ch 1 ch 1 ch 8 ch - Serial Interface I/O VDD External MIN. Value Expansion 1.8 V
PD78075B 32 K to 40 K 4 ch PD78078 PD78070A
48 K to 60 K -
2 ch 3 ch (UART: 1 ch)
88
61 3 ch (time-division UART: 1 ch) 3 ch (UART: 1 ch) 68 69
2.7 V 1.8 V 2.7 V 2.0 V
PD780058 24 K to 60 K 2 ch PD78058F 48 K to 60 K PD78054
16 K to 60 K - 2 ch 1 ch 8 ch - 4 ch 8 ch - 4 ch - - 8 ch
PD780065 40 K to 48 K PD780078 48 K to 60 K PD780034A 8 K to 32 K PD780024A PD780034AS PD780024AS PD78014H PD78018F 8 K to 60 K PD78083
8 K to 16 K - - - 1 ch - 8 ch
4 ch (UART: 1 ch) 3 ch (UART: 2 ch) 3 ch (UART: 1 ch)
60 52 51
2.7 V 1.8 V
39
-
2 ch
53
1 ch (UART: 1 ch) - 3 ch (UART: 2 ch)
33 47 4.0 V
- -
Inverter PD780988 16 K to 60 K 3 ch Note control VFD drive
PD780208 32 K to 60 K 2 ch PD780232 16 K to 24 K 3 ch PD78044H 32 K to 48 K 2 ch PD78044F 16 K to 40 K
1 ch - 1 ch
1 ch - 1 ch
1 ch
8 ch 4 ch 8 ch
-
-
2 ch
74 40
2.7 V 4.5 V 2.7 V
1 ch 2 ch
68
LCD drive
PD780354 24 K to 32 K 4 ch PD780344 PD780338 48 K to 60 K 3 ch PD780328 PD780318 PD780308 48 K to 60 K 2 ch PD78064B 32 K PD78064
16 K to 32 K 2 ch
1 ch
1 ch
1 ch
- 8 ch
8 ch -
-
3 ch (UART: 1 ch)
66
1.8 V
-
2 ch
-
10 ch 1 ch 2 ch (UART: 1 ch)
54 62 70
1 ch
8 ch
-
-
3 ch (time-division UART: 1 ch) 2 ch (UART: 1 ch)
57
2.0 V
Bus interface
PD780948 60 K PD78098B 40 K to 60 K
2 ch 1 ch 2 ch 2 ch
1 ch
1 ch
8 ch
-
- 2 ch
3 ch (UART: 1 ch)
79 69
4.0 V 2.7 V 4.0 V 2.2 V
-
supported PD780816 32 K to 60 K Meter control Dashboard control
12 ch - 1 ch - -
- -
2 ch (UART: 1 ch) 2 ch (UART: 1 ch)
46 69
PD780958 48 K to 60 K 4 ch PD780852 32 K to 40 K 3 ch PD780828B 32 K to 60 K
-
1 ch
1 ch
1 ch
5 ch
-
-
3 ch (UART: 1 ch)
56 59
4.0 V
-
Note 16-bit timer: 2 channels 10-bit timer: 1 channel
30
User's Manual U11302EJ4V0UM
CHAPTER 1
OUTLINE
1.7 Block Diagram
P00 P01 to P03 P04 P10 to P17
TO0/P30 TI0/P00
16-bit timer/ event counter
Port 0
TO1/P31 TI1/P33 TO2/P32 TI2/P34
8-bit timer/ event counter 1 8-bit timer/ event counter 2
Port 1
Port 2
P20 to P27
Watchdog timer
Port 3
P30 to P37
Watch timer
Port 7
P70 to P74
SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 ANI0/P10 to ANI7/P17 AVDD AVSS AVREF INTP0/P00 to INTP3/P03 BUZ/P36
Serial interface 0 78K/0 CPU core Serial interface 1 ROM
Port 8
P80 to P87
Port 9
P90 to P97
Port 10
P100 to P107
Port 11
P110 to P117
A/D converter RAM Interrupt control
Port 12
P120 to P127
VFD controller/ driver
FIP0 to FIP52
VLOAD RESET X1 X2 XT1/P04 XT2
Buzzer output Clock output control
PCL/P35
System control VDD VSS IC (VPP)
Remarks 1. The internal ROM and RAM capacities vary depending on the product. 2. Pin names in parentheses only apply to the PD78P0208.
User's Manual U11302EJ4V0UM
31
CHAPTER 1
OUTLINE
1.8 Overview of Functions
PD780204 PD780204A
Mask ROM
Part Number Item Internal memory ROM
PD780205 PD780205A
PD780206
PD780208
PD78P0208
One-time PROM
32 KBNote 1 High-speed RAM Expansion RAM Buffer RAM VFD display RAM General-purpose registers Minimum instruction execution time Instruction set With main system clock selected With subsystem clock selected * * * * 64 bytes 80 bytes 1024 bytes -
40 KBNote 1
48 KB
60 KB
60 KBNote 2
1024 bytes
1024 bytesNote 3
8 bits x 8 x 4 banks 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s (when operated at 5.0 MHz) 122 s (when operated at 32.768 kHz) 16-bit operation Multiply/divide (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, and Boolean operation) BCD adjust, and other related operations 74 pins 2 pins 27 pins 5 pins 24 pins
I/O ports (including VFD pins)
Total: * CMOS input: * CMOS I/O: * N-ch open-drain I/O: * P-ch open-drain I/O: *
P-ch open-drain output: 16 pins 53 pins 9 to 40 pins 2 to 16 pins
VFD controller/driver
Total of display output: * Segments: * Digits: * * * *
A/D converter
8-bit resolution x 8 channels Power supply voltage: AVDD = 4.0 to 5.5 V 3-wire serial I/O/SBI/2-wire serial I/O mode selection possible: 1 channel 3-wire serial I/O mode (maximum 64-byte on-chip automatic transmit/receive function): 1 channel
Serial interface
Notes 1. The initial value of the internal memory size switching register (IMS) in the PD780204A and 780205A is fixed to CFH (60 KB), regardless of the internal memory capacity. Therefore, set the values shown below for each product before use.
PD780204A: C8H (32 KB) PD780205A: CAH (40 KB)
2. 32, 40, 48, or 60 KB can be selected by the internal memory size switching register (IMS). 3. 0 or 1024 bytes can be selected by the internal expansion RAM size switching register (IXS).
32
User's Manual U11302EJ4V0UM
CHAPTER 1
OUTLINE
Part Number Item Timer
PD780204 PD780204A
PD780205 PD780205A
PD780206
PD780208
PD78P0208
* 16-bit timer/event counter: 1 channel * 8-bit timer/event counter: * Watch timer: * Watchdog timer: 2 channels 1 channel 1 channel
Timer output Clock output
3 outputs (14-bit PWM generation possible from one output) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz (@ 5.0 MHz operation with main system clock) 32.768 kHz (@ 32.768 kHz operation with subsystem clock)
Buzzer output
1.2 kHz, 2.4 kHz, 4.9 kHz (@ 5.0 MHz operation with main system clock) Maskable interrupts Internal: 9, external: 4
Vectored interrupt sources
Non-maskable interrupts Software interrupts
Internal: 1 1 Internal: 1 VDD = 2.7 to 5.5 V 100-pin plastic QFP (14 x 20)
Test input Power supply voltage Package
1.9 Mask Options
The mask ROM versions (PD780204, PD780204A, PD780205, PD780205A, PD780206, and PD780208) have mask options. By specifying the mask options when ordering, the pull-up resistors and pull-down resistors listed in Table 1-1 can be incorporated. When these resistors are necessary, the number of external components and mounting space can be saved by utilizing the mask options. Table 1-1 shows the mask options provided in the PD780208 Subseries products. Table 1-1. Mask Options in Mask ROM Versions
Pin Name P30/TO0 to P32/TO2, P33/TI1, P34/TI2, P35/PCL, P36/BUZ, P37 P70 to P74 FIP0 to FIP12 P80/FIP13 to P87/FIP20, P90/FIP21 to P97/FIP28, P100/FIP29 to P107/FIP36, P110/FIP37 to P117/FIP44, P120/FIP45 to P127/FIP52 Mask Option On-chip pull-down resistor can be specified in 1-bit units.
On-chip pull-up resistor can be specified in 1-bit units. On-chip pull-down resistor can be specified in 1-bit units. On-chip pull-down resistor can be specified in 1-bit units. The connect destination of a pull-down resistor can be specified for VLOAD or VSS in 4-bit units from P80.
Caution
Adjust the number of pull-down resistors so that the total power dissipation (refer to 15.10 Calculating Total Power Dissipation) is not exceeded.
User's Manual U11302EJ4V0UM
33
CHAPTER 2
PIN FUNCTIONS
2.1 Pin Function List
2.1.1 Normal operating mode pins (1) Port pins (1/2)
After Reset Input Input Alternate Function INTP0/TI0 INTP1 INTP2 INTP3 Input Input XT1 ANI0 to ANI7
Pin Name P00 P01 P02 P03 P04Note 1 P10 to P17
I/O Input I/O Port 0. 5-bit I/O port.
Function Input only Input/output can be specified in 1-bit units. If used as an input port, use of an on-chip pull-up resistor can be specified by software settings. Input only Port 1. 8-bit I/O port. Input/output can be specified in 1-bit units. If used as an input port, use of an on-chip pull-up resistor can be specified by software settingsNote 2. Port 2. 8-bit I/O port. Input/output can be specified in 1-bit units. If used as an input port, use of an on-chip pull-up resistor can be specified by software settings.
Input I/O
P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37
I/O
Input
SI1 SO1 SCK1 STB BUSY SI0/SB0 SO0/SB1 SCK0
I/O
Port 3. 8-bit I/O port. Input/output can be specified in 1-bit units. LEDs can be driven directly. If used as an input port, use of an on-chip pull-up resistor can be specified by software settings. In mask ROM versions, use of an on-chip pull-down resistor can be specified in 1-bit units with the mask option.
Input
TO0 TO1 TO2 TI1 TI2 PCL BUZ --
Notes 1. When the P04/XT1 pin is used as an input port, set bit 6 (FRC) of the processor clock control register (PCC) to 1 (do not use the feedback resistor contained in the subsystem clock oscillator). 2. When the P10/ANI0 to P17/ANI7 pins are used as analog inputs of the A/D converter, set port 1 to the input mode. In this case, its on-chip pull-up resistor will be automatically disabled.
34
User's Manual U11302EJ4V0UM
CHAPTER 2
PIN FUNCTIONS
(1) Port pins (2/2)
After Reset Input Alternate Function --
Pin Name P70 to P74
I/O I/O
Function Port 7. N-ch open-drain 5-bit I/O port. LEDs can be driven directly. Input/output can be specified in 1-bit units. In mask ROM versions, use of an on-chip pull-up resistor can be specified in 1-bit units with the mask option. Port 8. P-ch open-drain 8-bit high-withstanding-voltage output port. LEDs can be driven directly. In mask ROM versions, use of an on-chip pull-down resistor can be specified in 1-bit units with the mask option (connection to VLOAD or VSS is specifiable in 4-bit units). Port 9. P-ch open-drain 8-bit high-withstanding-voltage output port. LEDs can be driven directly. In mask ROM versions, use of an on-chip pull-down resistor can be specified in 1-bit units with the mask option (connection to VLOAD or VSS is specifiable in 4-bit units).
P80 to P87
Output
Output
FIP13 to FIP20
P90 to P97
Output
Output
FIP21 to FIP28
P100 to P107 I/O
Port 10. P-ch open-drain 8-bit high-withstanding-voltage I/O port. Input/output can be specified in 1-bit units. LEDs can be driven directly. In mask ROM versions, use of an on-chip pull-down resistor can be specified in 1-bit units with the mask option (connection to VLOAD or VSS is specifiable in 4-bit units). Port 11. P-ch open-drain 8-bit high-withstanding-voltage I/O port. Input/output can be specified in 1-bit units. LEDs can be driven directly. In mask ROM versions, use of an on-chip pull-down resistor can be specified in 1-bit units with the mask option (connection to VLOAD or VSS is specifiable in 4-bit units).
Input
FIP29 to FIP36
P110 to P117 I/O
Input
FIP37 to FIP44
P120 to P127 I/O
Port 12. P-ch open-drain 8-bit high-withstanding-voltage I/O port. Input/output can be specified in 1-bit units. LEDs can be driven directly. In mask ROM versions, use of an on-chip pull-down resistor can be specified in 1-bit units with the mask option (connection to VLOAD or VSS is specifiable in 4-bit units).
Input
FIP45 to FIP52
User's Manual U11302EJ4V0UM
35
CHAPTER 2
PIN FUNCTIONS
(2) Non-port pins (1/2)
After Reset Input Alternate Function P00/TI0 P01 P02 External interrupt request input with falling edge detection Input Serial interface serial data input Input P03 P25/SB0 P20 Output Serial interface serial data output Input P26/SB1 P21 I/O Serial interface serial data input/output Input P25/SI0 P26/SO0 I/O Serial interface serial clock input/output Input P27 P22 Output Input Input Serial interface automatic transmit/receive strobe output Serial interface automatic transmit/receive busy input Input of external count clock to 16-bit timer (TM0) Input of external count clock to 8-bit timer (TM1) Input of external count clock to 8-bit timer (TM2) Output 16-bit timer (TM0) output (also used for 14-bit PWM output) 8-bit timer (TM1) output 8-bit timer (TM2) output Output Output Output Clock output (for trimming main system clock and subsystem clock) Buzzer output Input Input Input Input Input Input P23 P24 P00/INTP0 P33 P34 P30 P31 P32 P35 P36 --
Pin Name INTP0 INTP1 INTP2 INTP3 SI0 SI1 SO0 SO1 SB0 SB1 SCK0 SCK1 STB BUSY TI0 TI1 TI2 TO0 TO1 TO2 PCL BUZ FIP0 to FIP12
I/O Input
Function External interrupt request inputs for which the valid edges (rising edge, falling edge, or both rising and falling edges) can be specified.
High withstanding voltage and high current output for VFD controller/ Output driver display output. In mask ROM versions, use of an on-chip pull-down resistor can be specified with the mask option. The PD78P0208 has on-chip pull-down resistors (connected to VLOAD). High withstanding voltage and high current output for VFD controller/ Output driver display output. In mask ROM versions, use of an on-chip pull-down resistor can be Input specified with the mask option. The PD78P0208 has no on-chip pull-down resistors.
FIP13 to FIP20 FIP21 to FIP28 FIP29 to FIP36 FIP37 to FIP44 FIP45 to FIP52 VLOAD ANI0 to ANI7 AVREF AVDD AVSS RESET
Output
P80 to P87 P90 to P97 P100 to P107 P110 to P117 P120 to P127
-- Input Input -- -- Input
Pull-down resistor connection for VFD controller/driver A/D converter analog input A/D converter reference voltage input A/D converter analog power supply. Connect to VDD. A/D converter ground potential. Connect to VSS. System reset input
-- Input -- -- -- --
-- P10 to P17 -- -- -- --
36
User's Manual U11302EJ4V0UM
CHAPTER 2
PIN FUNCTIONS
(2) Non-port pins (2/2)
After Reset -- -- Crystal resonator connection for subsystem clock oscillation Input -- Positive power supply High-voltage application for program write/verify. Connect directly to VSS in normal operation mode. Ground potential Internally connected. Connect directly to VSS. -- -- P04 -- -- -- Alternate Function -- --
Pin Name X1 X2 XT1 XT2 VDD VPP
I/O Input -- Input -- -- --
Function Crystal resonator connection for main system clock oscillation
VSS IC
-- --
-- --
-- --
2.1.2 PROM programming mode pins (PD78P0208 only)
Pin Name RESET
I/O Input
Function PROM programming mode setting. When +5 V or +12.5 V is applied to the VPP pin or a low-level voltage is applied to the RESET pin, the PROM programming mode is set. High-voltage application for PROM programming mode setting and program write/verify Address bus Data bus PROM enable input/program pulse input Read strobe input to PROM Program/program inhibit input in PROM programming mode Positive power supply Ground potential
VPP A0 to A16 D0 to D7 CE OE PGM VDD VSS
Input Input I/O Input Input Input -- --
User's Manual U11302EJ4V0UM
37
CHAPTER 2
PIN FUNCTIONS
2.2 Description of Pin Functions
2.2.1 P00 to P04 (Port 0) These pins constitute a 5-bit I/O port. Besides serving as I/O port pins, they function as external interrupt request inputs, an external count clock input to the timer, a capture trigger signal input, and crystal resonator connection for subsystem clock oscillation. The following operating modes can be specified in 1-bit units. (1) Port mode P00 and P04 function as input-only port pins and P01 to P03 function as I/O port pins. P01 to P03 can be specified in input or output mode in 1-bit units using port mode register 0 (PM0). When they are used as input port pins, an on-chip pull-up resistor can be used by setting the pull-up resistor option register (PUO). (2) Control mode P00 to P04 function as external interrupt request inputs, an external count clock input to the timer, and crystal connection for subsystem clock oscillation. (a) INTP0 to INTP3 INTP0 to INTP2 are external interrupt request input pins for which valid edges can be specified (rising edge, falling edge, and both rising and falling edges). INTP0 becomes a 16-bit timer/event counter capture trigger signal input pin with a valid edge input. INTP3 becomes a falling edge detection external interrupt request input pin. (b) TI0 TI0 is a pin for inputting the external count clock to the 16-bit timer/event counter. (c) XT1 Crystal connection pin for subsystem clock oscillation 2.2.2 P10 to P17 (Port 1) These pins constitute an 8-bit I/O port. Besides serving as I/O port pins, they function as A/D converter analog inputs. The following operating modes can be specified in 1-bit units. (1) Port mode P10 to P17 function as an 8-bit I/O port. They can be specified in input or output mode in 1-bit units using port mode register 1 (PM1). When they are used as input port pins, an on-chip pull-up resistor can be used by setting the pull-up resistor option register (PUO). (2) Control mode P10 to P17 function as A/D converter analog input pins (ANI0 to ANI7). The on-chip pull-up resistors are automatically disabled when the pins are specified for analog input.
38
User's Manual U11302EJ4V0UM
CHAPTER 2
PIN FUNCTIONS
2.2.3 P20 to P27 (Port 2) These pins constitute an 8-bit I/O port. Besides serving as I/O port pins, they function as serial interface data I/ O, clock I/O, automatic transmit/receive busy input, and strobe output pins. The following operating modes can be specified in 1-bit units. (1) Port mode P20 to P27 function as an 8-bit I/O port. They can be specified in input or output mode in 1-bit units using port mode register 2 (PM2). When they are used as input port pins, an on-chip pull-up resistor can be used by setting the pull-up resistor option register (PUO). (2) Control mode P20 to P27 function as serial interface data I/O, clock I/O, automatic transmit/receive busy input, and strobe output pins. (a) SI0, SI1, SO0, SO1 Serial interface serial data I/O pins (b) SCK0 and SCK1 Serial interface serial clock I/O pins (c) SB0 and SB1 NEC Electronics standard serial bus interface I/O pins (d) BUSY Serial interface automatic transmit/receive busy input pin (e) STB Serial interface automatic transmit/receive strobe output pin Caution If port 2 is used as serial interface pins, the I/O and output latches must be set according to the function. For the setting method, refer to Figure 13-3 Format of Serial Operating Mode Register 0 and Figure 14-3 Format of Serial Operating Mode Register 1. 2.2.4 P30 to P37 (Port 3) These pins constitute an 8-bit I/O port. Besides serving as I/O port pins, they function as timer I/O, clock output, and buzzer output pins. In mask ROM versions, use of pull-down resistors can be specified with the mask option. Port 3 can drive LEDs directly. The following operating modes can be specified in 1-bit units. (1) Port mode P30 to P37 function as an 8-bit I/O port. They can be specified in input or output mode in 1-bit units using port mode register 3 (PM3). When they are used as input port pins, an on-chip pull-up resistor can be used by setting the pull-up resistor option register (PUO).
User's Manual U11302EJ4V0UM
39
CHAPTER 2
PIN FUNCTIONS
(2) Control mode P30 to P37 function as timer I/O, clock output, and buzzer output pins. (a) TI1 and TI2 Pins for external count clock input to the 8-bit timer/event counter. (b) TO0 to TO2 Timer output pins (c) PCL Clock output pin (d) BUZ Buzzer output pin 2.2.5 P70 to P74 (Port 7) These pins constitute a 5-bit I/O port. They can be specified in input or output mode in 1-bit units using port mode register 7 (PM7). Port 7 can drive LEDs directly. P70 to P74 are N-ch open-drain outputs. In mask ROM versions, use of pull-up resistors can be specified with the mask option. 2.2.6 P80 to P87 (Port 8) These pins constitute an 8-bit output-only port. Besides serving as output port pins, they function as display outputs for the VFD controller/driver. Port 8 can drive LEDs directly. The following operating modes can be specified in 1-bit units. (1) Port mode P80 to P87 function as an 8-bit output-only port. P80 to P87 are P-ch open-drain outputs. In mask ROM versions, use of pull-down resistors can be specified with the mask option. (2) Control mode P80 to P87 function as the display output pins of the VFD controller/driver (FIP13 to FIP20). 2.2.7 P90 to P97 (Port 9) These pins constitute an 8-bit output-only port. Besides serving as output port pins, they function as display outputs for the VFD controller/driver. Port 9 can drive LEDs directly. The following operating modes can be specified in 1-bit units. (1) Port mode P90 to P97 function as an 8-bit output-only port. P90 to P97 are P-ch open-drain outputs. In mask ROM versions, use of pull-down resistors can be specified with the mask option. (2) Control mode P90 to P97 function as the display output pins of the VFD controller/driver (FIP21 to FIP28).
40
User's Manual U11302EJ4V0UM
CHAPTER 2
PIN FUNCTIONS
2.2.8 P100 to P107 (Port 10) These pins constitute an 8-bit I/O port. Besides serving as I/O port pins, they function as display outputs for the VFD controller/driver. Port 10 can drive LEDs directly. The following operating modes can be specified in 1-bit units. (1) Port mode P100 to P107 function as an 8-bit I/O port. They can be specified in input or output mode in 1-bit units using port mode register 10 (PM10). P100 to P107 are P-ch open-drain outputs. In mask ROM versions, use of pull-down resistors can be specified with the mask option. (2) Control mode P100 to P107 function as display output pins for the VFD controller/driver (FIP29 to FIP36). 2.2.9 P110 to P117 (Port 11) These pins constitute an 8-bit I/O port. Besides serving as I/O port pins, they function as display outputs for the VFD controller/driver. Port 11 can drive LEDs directly. The following operating modes can be specified in 1-bit units. (1) Port mode P110 to P117 function as an 8-bit I/O port. They can be specified in input or output mode in 1-bit units using port mode register 11 (PM11). P110 to P117 are P-ch open-drain outputs. In mask ROM versions, use of pull-down resistors can be specified with the mask option. (2) Control mode P110 to P117 function as display output pins for the VFD controller/driver (FIP37 to FIP44). 2.2.10 P120 to P127 (Port 12) These pins constitute an 8-bit I/O port. Besides serving as I/O port pins, they function as display outputs for the VFD controller/driver. Port 12 can drive LEDs directly. The following operating modes can be specified in 1-bit units. (1) Port mode P120 to P127 function as an 8-bit I/O port. They can be specified in input or output mode in 1-bit units using port mode register 12 (PM12). P120 to P127 are P-ch open-drain outputs. In mask ROM versions, use of pull-down resistors can be specified with the mask option. (2) Control mode P120 to P127 function as display output pins for the VFD controller/driver (FIP45 to FIP52). 2.2.11 FIP0 to FIP12 These are display output pins for the VFD controller/driver. FIP0 to FIP12 are P-ch open-drain outputs. In mask ROM versions, use of pull-down resistors can be specified with the mask option. The PD78P0208 contains pull-down resistors at FIP0 to FIP12 (connected to VLOAD).
User's Manual U11302EJ4V0UM
41
CHAPTER 2
PIN FUNCTIONS
2.2.12 VLOAD This is the pull-down resistor connection pin of the VFD controller/driver. 2.2.13 AVREF The A/D converter's reference voltage should be input from this pin. 2.2.14 AVDD This pin supplies power for A/D converter operations. Always make this pin the same potential as the VDD pin even if the A/D converter is not used. 2.2.15 AVSS This pin is the ground for the A/D converter. Always make this pin the same potential as the VSS pin even if the A/D converter is not used. 2.2.16 RESET This is an active-low system reset input pin. 2.2.17 X1 and X2 These are crystal resonator connection pins for main system clock oscillation. For external clock supply, input the clock to X1 and its inverted signal to X2. 2.2.18 XT1 and XT2 These are crystal resonator connection pins for subsystem clock oscillation. For external clock supply, input the clock to XT1 and its inverted signal to XT2. 2.2.19 VDD This is the positive power supply pin. 2.2.20 VSS This is the ground potential pin. 2.2.21 VPP (PD78P0208 only) A high-voltage should be applied to this pin during PROM programming mode setting and in program write/verify mode. Connect directly to VSS in normal operation mode. 2.2.22 IC (mask ROM version only) The IC (Internally Connected) pin sets a test mode in which the PD780204, 780204A, 780205, 780205A, 780206, and 780208 are tested before shipment. In normal operation mode, connect the IC pin directly to the VSS pin with as short a wiring length as possible. If there is a potential difference between the IC and VSS pins because the wiring length between the IC and VSS pins is too long, or external noise is superimposed on the IC pin, the user program may not run correctly. * Directly connect the IC pin to the VSS pin.
VSS IC
Keep the wiring length as short as possible.
42
User's Manual U11302EJ4V0UM
CHAPTER 2
PIN FUNCTIONS
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-1 shows the I/O circuit types of pins and the recommended connections of unused pins. Refer to Figure 2-1 for the configuration of the I/O circuit of each type. Table 2-1. Types of Pin I/O Circuits (1/2)
Pin Name I/O Circuit Type 2 8-A I/O Recommended Connection of Unused Pins
P00/INTP0/TI0 P01/INTP1 P02/INTP2 P03/INTP3 P04/XT1 P10/ANI0 to P17/ANI7 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 Mask ROM version P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37
Input I/O
Connect to VSS. Input: Independently connect to VSS via a resistor. Output: Leave open.
16 11 8-A 5-A 8-A 5-A 8-A 10-A
Input I/O
Connect to VDD or VSS. Input: Independently connect to VDD or VSS via a resistor. Output: Leave open.
5-C
I/O
Input: Independently connect to VDD or VSS via a resistorNote. Output: Leave open.
8-B
5-C
Note
Leave open when an on-chip pull-down resistor is specified by the mask option.
User's Manual U11302EJ4V0UM
43
CHAPTER 2
PIN FUNCTIONS
Table 2-1. Types of Pin I/O Circuits (2/2)
Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins
PD78P0208
P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 Mask ROM version P70 to P74 13-B I/O Input: Independently connect to VDD or VSS via a resistorNote. Output: Leave open. Leave open. 5-A 8-A 5-A I/O Input: Independently connect to VDD or VSS via a resistor. Output: Leave open.
FIP0 to FIP12 P80/FIP13 to P87/FIP20 P90/FIP21 to P97/FIP28 P100/FIP29 to P107/FIP36 P110/FIP37 to P117/FIP44 P120/FIP45 to P127/FIP52 IC
14-A
Output
15-C
I/O
Input: Independently connect to VDD or VSS via a resistorNote. Output: Leave open.
--
--
Connect directly to VSS.
PD78P0208
P70 to P74 13-D I/O Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. Leave open. Leave open.
FIP0 to FIP12 P80/FIP13 to P87/FIP20 P90/FIP21 to P97/FIP28 P100/FIP29 to P107/FIP36 P110/FIP37 to P117/FIP44 P120/FIP45 to P127/FIP52 VPP RESET XT2 AVREF AVDD AVSS VLOAD
14 14-B
Output Output
15-B
I/O
Input: Independently connect to VDD or VSS via a resistor. Output: Leave open.
-- 2 16 --
-- Input --
Connect directly to VSS. -- Leave open. Connect directly to VSS. Connect directly to VDD. Connect directly to VSS.
Note
Leave open when an on-chip pull-up or pull-down resistor is specified by the mask option.
44
User's Manual U11302EJ4V0UM
CHAPTER 2
PIN FUNCTIONS
Figure 2-1. Pin I/O Circuits (1/3)
Type 2 Type 8-A
VDD
Pull-up enable IN VDD Data Schmitt-triggered input with hysteresis characteristics Output disable N-ch P-ch
P-ch
IN/OUT
Type 5-A
VDD
Type 8-B VDD
Pull-up enable VDD
P-ch
Pull-up enable VDD
P-ch
Data
P-ch IN/OUT
Data
P-ch IN/OUT
Output disable
N-ch
Output disable
N-ch
Mask option
Input enable Type 5-C VDD Type 10-A VDD Pull-up enable VDD Data P-ch IN/OUT IN/OUT Output disable N-ch Mask option Open drain Output disable N-ch
P-ch
Pull-up enable VDD Data P-ch
P-ch
Input enable
User's Manual U11302EJ4V0UM
45
CHAPTER 2
PIN FUNCTIONS
Figure 2-1. Pin I/O Circuits (2/3)
Type 11 Pull-up enable Data VDD P-ch VDD P-ch IN/OUT Output disable Comparator + - N-ch VREF (Threshold voltage) Input enable Type 13-B Mask option Data Output disable N-ch VDD Data N-ch Mask option VLOAD N-ch P-ch N-ch VLOAD Data P-ch P-ch OUT VDD VDD Type 14
VDD
Type 14-A
VDD IN/OUT P-ch
VDD
P-ch OUT
RD
P-ch
Middle-voltage input buffer
Mask option
Type 13-D
Type 14-B
IN/OUT Data Output disable VDD Data RD P-ch N-ch OUT N-ch VDD P-ch VDD P-ch
Middle-voltage input buffer
46
User's Manual U11302EJ4V0UM
CHAPTER 2
PIN FUNCTIONS
Figure 2-1. Pin I/O Circuits (3/3)
Type 15-B VDD P-ch Data N-ch VDD P-ch IN/OUT Feedback cut-off P-ch Type 16
RD
N-ch
XT1
XT2
Type 15-C VDD P-ch Data N-ch VDD P-ch IN/OUT
RD
N-ch
Mask option VLOAD
Mask option
User's Manual U11302EJ4V0UM
47
CHAPTER 3
CPU ARCHITECTURE
3.1 Memory Space
Each product of the PD780208 Subseries accesses a memory space of 64 KB. Figures 3-1 to 3-5 show memory maps. Caution The initial values of the internal memory size switching register (IMS) in the PD780204A, 780205A, and 78P0208 are fixed to CFH, regardless of the internal memory capacity. Therefore, set the values shown below for each product before use.
PD780204A: C8H PD780205A: CAH PD78P0208: Value corresponding to mask ROM version
Figure 3-1. Memory Map (PD780204 and PD780204A)
FFFFH Special-function registers (SFRs) 256 x 8 bits FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits
Internal high-speed RAM 1024 x 8 bits 7FFFH Program area 1000H 0FFFH CALLF entry area 0800H 07FFH Program area 0080H 007FH CALLT table area 0040H 003FH Vector table area 0000H
FB00H FAFFH Data memory space Buffer RAM 64 x 8 bits FAC0H FABFH Reserved FA80H FA7FH VFD display RAM 80 x 8 bits FA30H FA2FH Reserved 8000H 7FFFH Program memory space 0000H Internal ROM 32768 x 8 bits
48
User's Manual U11302EJ4V0UM
CHAPTER 3
CPU ARCHITECTURE
Figure 3-2. Memory Map (PD780205 and PD780205A)
FFFFH Special-function registers (SFRs) 256 x 8 bits FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits
Internal high-speed RAM 1024 x 8 bits 9FFFH Program area Buffer RAM 64 x 8 bits FAC0H FABFH Reserved FA80H FA7FH VFD display RAM 80 x 8 bits FA30H FA2FH Reserved A000H 9FFFH Program memory space 0000H Internal ROM 40960 x 8 bits 0040H 003FH Vector table area 0000H 0080H 007FH CALLT table area 0800H 07FFH Program area 1000H 0FFFH CALLF entry area
FB00H FAFFH Data memory space
User's Manual U11302EJ4V0UM
49
CHAPTER 3
CPU ARCHITECTURE
Figure 3-3. Memory Map (PD780206)
FFFFH Special-function registers (SFRs) 256 x 8 bits FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits
Internal high-speed RAM 1024 x 8 bits FB00H FAFFH FAC0H FABFH Data memory space FA80H FA7FH FA30H FA2FH F800H F7FFH F400H F3FFH
BFFFH Buffer RAM 64 x 8 bits Reserved VFD display RAM 80 x 8 bits Reserved Internal expansion RAM 1024 x 8 bits 0080H 007FH CALLT table area 0040H 003FH Vector table area 0000H 0800H 07FFH Program area 1000H 0FFFH CALLF entry area Program area
Reserved C000H BFFFH Program memory space 0000H Internal ROM 49152 x 8 bits
50
User's Manual U11302EJ4V0UM
CHAPTER 3
CPU ARCHITECTURE
Figure 3-4. Memory Map (PD780208)
FFFFH Special-function registers (SFRs) 256 x 8 bits FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits
Internal high-speed RAM 1024 x 8 bits FB00H FAFFH FAC0H FABFH Data memory space FA80H FA7FH FA30H FA2FH F800H F7FFH F400H F3FFH
EFFFH Buffer RAM 64 x 8 bits Reserved VFD display RAM 80 x 8 bits Reserved Internal expansion RAM 1024 x 8 bits 0080H 007FH CALLT table area 0040H 003FH Vector table area 0000H 0800H 07FFH Program area 1000H 0FFFH CALLF entry area Program area
Reserved F000H EFFFH Program memory space 0000H Internal ROM 61440 x 8 bits
User's Manual U11302EJ4V0UM
51
CHAPTER 3
CPU ARCHITECTURE
Figure 3-5. Memory Map (PD78P0208)
FFFFH Special-function registers (SFRs) 256 x 8 bits FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits
Internal high-speed RAM 1024 x 8 bits FB00H FAFFH FAC0H FABFH FA80H FA7FH FA30H FA2FH F800H F7FFH F400H F3FFH Reserved F000H EFFFH Program memory space 0000H Internal PROM 61440 x 8 bits 0040H 003FH Vector table area 0000H EFFFH Buffer RAM 64 x 8 bits Reserved VFD display RAM 80 x 8 bits Reserved Internal expansion RAM 1024 x 8 bits 0080H 007FH CALLT table area 1000H 0FFFH CALLF entry area 0800H 07FFH Program area Program area
Data memory space
52
User's Manual U11302EJ4V0UM
CHAPTER 3
CPU ARCHITECTURE
3.1.1 Internal program memory space The internal program memory space stores programs and table data. Normally, this space is addressed using the program counter (PC). Each product in the PD780208 Subseries contains internal ROM (or PROM) with the capacity shown below. Table 3-1. Internal ROM Capacity
Internal ROM Part Number Configuration Capacity 32768 x 8 bits
PD780204 PD780204A PD780205 PD780205A PD780206 PD780208 PD78P0208
Mask ROM
Mask ROM
40960 x 8 bits
Mask ROM Mask ROM PROM
49152 x 8 bits 61440 x 8 bits 61440 x 8 bits
The following areas are allocated to the internal program memory space. (1) Vector table area The 64-byte area 0000H to 003FH is reserved as vector table area. Program start addresses for branch upon RESET input or interrupt request generation are stored in the vector table area. Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. Table 3-2. Vector Table
Vector Table Address 0000H 0004H 0006H 0008H 000AH 000CH 000EH Interrupt Source RESET input INTWDT INTP0 INTP1 INTP2 INTP3 INTCSI0 Vector Table Address 0010H 0012H 0014H 0016H 0018H 001AH 001CH 003EH Interrupt Source INTCSI1 INTTM3 INTTM0 INTTM1 INTTM2 INTAD INTKS BRK instruction
(2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
User's Manual U11302EJ4V0UM
53
CHAPTER 3
CPU ARCHITECTURE
3.1.2 Internal data memory space The PD780208 Subseries units incorporate the following RAMs. (1) Internal high-speed RAM Internal high-speed RAM is allocated to the 1024-byte area from FB00H to FEFFH of the PD780208 Subseries. Four banks of general-purpose registers, each bank consisting of eight 8-bit registers are allocated in the 32byte area FEE0H to FEFFH. This area cannot be used as a program area in which instructions are written and executed. The internal high-speed RAM can also be used as a stack memory. (2) Internal expansion RAM Internal expansion RAM is allocated to the 1024-byte area from F400H to F7FFH of the PD780206, 780208, and 78P0208. This area can also be used as a normal data area similar to the internal high-speed RAM, as well as a program area in which instructions can be written and executed. The internal expansion RAM cannot be used as a stack memory. (3) Buffer RAM Buffer RAM is allocated to the 64-byte area from FAC0H to FAFFH. Buffer RAM is used for storing transmit/ receive data of serial interface channel 1 (3-wire serial I/O mode with automatic transmit/receive function). When not used in the 3-wire serial I/O mode with automatic transmit/receive function, buffer RAM can be used as normal RAM. (4) VFD display RAM VFD display RAM is allocated to the 80-byte area from FA30H to FA7FH. VFD display RAM can also be used as normal RAM. 3.1.3 Special-function register (SFR) area On-chip peripheral hardware special-function registers (SFRs) are allocated to the area FF00H to FFFFH (see Table 3-3 Special-Function Register List under 3.2.3 Special-function registers (SFRs)). Caution Do not access addresses where SFRs are not assigned.
54
User's Manual U11302EJ4V0UM
CHAPTER 3
CPU ARCHITECTURE
3.1.4 Data memory addressing The method to specify the address of the instruction to be executed next or the address of a register or memory area to be manipulated when an instruction is executed is called addressing. The address of the instruction to be executed next is specified by the program counter (PC) (for details, refer to 3.3 Instruction Address Addressing). To address the memory area to be manipulated when an instruction is executed, the PD780208 Subseries has many addressing modes to improve the operability. Especially, in the areas to which the data memory is assigned (addresses FB00H to FFFFH), the special-function registers (SFRs) and general-purpose registers can be addressed in accordance with thier function. Data memory addressing is shown in Figures 3-6 to 3-10. For details of each addressing, refer to 3.4 Operand Address Addressing. Figure 3-6. Data Memory Addressing (PD780204 and PD780204A)
FFFFH Special-function registers (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Register addressing Short direct addressing Direct addressing Register indirect addressing Based addressing Based indexed addressing Buffer RAM 64 x 8 bits
SFR addressing
Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH FAC0H FABFH
Reserved FA80H FA7FH VFD display RAM 80 x 8 bits
FA30H FA2FH
Reserved 8000H 7FFFH Internal ROM 32768 x 8 bits 0000H
User's Manual U11302EJ4V0UM
55
CHAPTER 3
CPU ARCHITECTURE
Figure 3-7. Data Memory Addressing (PD780205 and PD780205A)
FFFFH Special-function registers (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH Buffer RAM 64 x 8 bits FAC0H FABFH Reserved FA80H FA7FH VFD display RAM 80 x 8 bits FA30H FA2FH Reserved A000H 9FFFH Internal ROM 40960 x 8 bits 0000H Register addressing Short direct addressing
SFR addressing
Direct addressing Register indirect addressing Based addressing Based indexed addressing
56
User's Manual U11302EJ4V0UM
CHAPTER 3
CPU ARCHITECTURE
Figure 3-8. Data Memory Addressing (PD780206)
FFFFH Special-function registers (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH FEE0H FEDFH Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH FAC0H FABFH FA80H FA7FH FA30H FA2FH F800H F7FFH F400H F3FFH Reserved C000H BFFFH Internal ROM 49152 x 8 bits 0000H SFR addressing
General-purpose registers 32 x 8 bits
Register addressing
Short direct addressing
Buffer RAM 64 x 8 bits Reserved VFD display RAM 80 x 8 bits Reserved Internal expansion RAM 1024 x 8 bits
Direct addressing Register indirect addressing Based addressing Based indexed addressing
User's Manual U11302EJ4V0UM
57
CHAPTER 3
CPU ARCHITECTURE
Figure 3-9. Data Memory Addressing (PD780208)
FFFFH Special-function registers (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH FEE0H FEDFH Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH FAC0H FABFH FA80H FA7FH FA30H FA2FH F800H F7FFH F400H F3FFH Reserved F000H EFFFH Internal ROM 61440 x 8 bits 0000H SFR addressing
General-purpose registers 32 x 8 bits
Register addressing
Short direct addressing
Buffer RAM 64 x 8 bits Reserved VFD display RAM 80 x 8 bits Reserved Internal expansion RAM 1024 x 8 bits
Direct addressing Register indirect addressing Based addressing Based indexed addressing
58
User's Manual U11302EJ4V0UM
CHAPTER 3
CPU ARCHITECTURE
Figure 3-10. Data Memory Addressing (PD78P0208)
FFFFH Special-function registers (SFRs) 256 x 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers 32 x 8 bits FEE0H FEDFH Internal high-speed RAM 1024 x 8 bits FE20H FE1FH FB00H FAFFH FAC0H FABFH FA80H FA7FH FA30H FA2FH F800H F7FFH F400H F3FFH Reserved F000H EFFFH Internal PROM 61440 x 8 bits 0000H Register addressing Short direct addressing
SFR addressing
Buffer RAM 64 x 8 bits Reserved VFD display RAM 80 x 8 bits Reserved Internal expansion RAM 1024 x 8 bits
Direct addressing Register indirect addressing Based addressing Based indexed addressing
User's Manual U11302EJ4V0UM
59
CHAPTER 3
CPU ARCHITECTURE
3.2 Processor Registers
The PD780208 Subseries units incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses, and stack memory. The program counter (PC), program status word (PSW), and stack pointer (SP) are control registers. (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data and register contents are set. RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter. Figure 3-11. Program Counter Format
15 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 0 PC0
(2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically reset upon execution of the RETB, RETI, and POP PSW instructions. RESET input sets the PSW to 02H. Figure 3-12. Program Status Word Format
7 PSW IE Z RBS1 AC RBS0 0 ISP 0 CY
(a) Interrupt enable flag (IE) This flag controls interrupt request acknowledgment operations of the CPU. When IE = 0, the IE flag is set to the interrupt disabled (DI) status. All interrupts except non-maskable interrupts are disabled. When IE = 1, the IE flag is set to the interrupt enabled (EI) status and interrupt request acknowledgment is controlled by an in-service priority flag (ISP), an interrupt mask flag for each interrupt source, and a priority specification flag. This flag is reset to (0) upon DI instruction execution or interrupt request acknowledgment and is set to (1) upon EI instruction execution. (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags used to select one of the four register banks. In these flags, the 2-bit information which indicates the register bank selected by SEL RBn instruction execution is stored.
60
User's Manual U11302EJ4V0UM
CHAPTER 3
CPU ARCHITECTURE
(d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flag (ISP) This flag manages the priority of acknowledgeable maskable vectored interrupts. When ISP = 0, acknowledgment of a vectored interrupt request specified as lower priority by the priority specification flag registers (PR0L and PR0H) (refer to 16.3 (3) Priority specification flag registers (PR0L, PR0H)) is disabled. Whether the interrupt request is actually acknowledged or not is controlled by the interrupt enable flag (IE). (f) Carry flag (CY) This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution. (3) Stack pointer (SP) This is a 16-bit register used to hold the start address of the memory stack area. Only the internal high-speed RAM area (FB00H to FEFFH) can be set as the stack area. Figure 3-13. Stack Pointer Format
15 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 0 SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory. Each stack operation saves/resets data as shown in Figures 3-14 and 3-15. Caution Because RESET input makes SP contents undefined, be sure to initialize the SP before instruction execution.
User's Manual U11302EJ4V0UM
61
CHAPTER 3
CPU ARCHITECTURE
Figure 3-14. Data to Be Saved to Stack Memory
Interrupt and BRK instruction SP SP SP - 2 SP - 2 SP - 1 SP Lower register pairs Higher register pairs SP SP - 2 SP - 2 SP - 1 SP PC7 to PC0 PC15 to PC8 SP - 3 SP - 3 SP - 2 SP - 1 SP PC7 to PC0 PC15 to PC8 PSW
PUSH rp instruction
CALL, CALLF, and CALLT instructions
Figure 3-15. Data to Be Reset from Stack Memory
POP rp instruction
RET instruction
RETI and RETB instructions
SP SP + 1 SP SP + 2
Lower register pairs Higher register pairs SP
SP SP + 1 SP + 2
PC7 to PC0 PC15 to PC8
SP SP + 1 SP + 2 SP SP + 3
PC7 to PC0 PC15 to PC8 PSW
62
User's Manual U11302EJ4V0UM
CHAPTER 3
CPU ARCHITECTURE
3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. They consist of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can be used in pairs as a 16-bit register (AX, BC, DE, and HL). They can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Register banks to be used for instruction execution are set using the CPU control instruction (SEL RBn). Because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank. Figure 3-16. General-Purpose Register Configuration (a) Absolute name
16-bit processing FEFFH R7 BANK0 FEF8H R5 BANK1 FEF0H BANK2 FEE8H BANK3 FEE0H 15 0 7 RP0 R0 0 RP1 R2 R1 RP2 R4 R3 RP3 R6 8-bit processing
(b) Function name
16-bit processing FEFFH H BANK0 FEF8H D BANK1 FEF0H BANK2 FEE8H BANK3 FEE0H 15 0 7 AX X 0 BC C A DE E B HL L 8-bit processing
User's Manual U11302EJ4V0UM
63
CHAPTER 3
CPU ARCHITECTURE
3.2.3 Special-function registers (SFRs) Unlike a general-purpose register, each special-function register has a special function. The special-function registers are allocated in the FF00H to FFFFH area. Special-function registers can be manipulated, like general-purpose registers, with operation, transfer, and bit manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special-function register type. Each manipulation bit unit can be specified as follows. * 1-bit manipulation Describe the symbol reserved in the assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address. * 8-bit manipulation Describe the symbol reserved in the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address. * 16-bit manipulation Describe the symbol reserved in the assembler for the 16-bit manipulation instruction operand (sfrp). When addressing an address, describe an even address. Table 3-3 gives a list of special-function registers. The meaning of items in the table is as follows. * Symbol Indicates symbols that specify the addresses of the special-function registers. The RA78K0 uses these symbols as reserved words, and the CC78K0 defines them in the header file "sfrbit.h". Symbols can be used as instruction operands if the RA78K0, ID78K0, or SD78K0 is used. * R/W Indicates whether the corresponding special-function register can be read or written. R/W: Read/write enable R: W: Read only Write only
* Manipulatable bit units indicates manipulatable bit units (1, 8, and 16). - indicates unmanipulatable bit units. * After reset Indicates each register status upon RESET input.
64
User's Manual U11302EJ4V0UM
CHAPTER 3
CPU ARCHITECTURE
Table 3-3. Special-Function Register List (1/3)
Address Special-Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit
1 Bit 8 Bits 16 Bits
After Reset
FF00H FF01H FF02H FF03H FF07H FF08H FF09H FF0AH FF0BH FF0CH FF10H FF11H FF12H FF13H FF14H FF15H FF16H FF17H FF18H FF19H FF1AH FF1BH FF1FH FF20H FF21H FF22H FF23H FF27H FF2AH FF2BH FF2CH FF40H FF41H FF42H FF43H FF47H FF48H FF49H FF4AH FF4EH FF4FH
Port 0 Port 1 Port 2 Port 3 Port 7 Port 8 Port 9 Port 10 Port 11 Port 12 16-bit compare register
P0 P1 P2 P3 P7 P8 P9 P10 P11 P12 CR00
R/W

-
- - - - - - - - - -
00H
W

-
R/W

- -
Undefined
16-bit capture register
CR01
R
- -
- -

16-bit timer register
TM0
0000H
8-bit compare register 10 8-bit compare register 20 8-bit timer register 1 8-bit timer register 2 Serial I/O shift register 0 Serial I/O shift register 1 A/D conversion result register Port mode register 0 Port mode register 1 Port mode register 2 Port mode register 3 Port mode register 7 Port mode register 10 Port mode register 11 Port mode register 12 Timer clock select register 0 Timer clock select register 1 Timer clock select register 2 Timer clock select register 3 Sampling clock select register 16-bit timer mode control register 8-bit timer mode control register Watch timer mode control register 16-bit timer output control register 8-bit timer output control register
CR10 CR20 TMS TM1 TMS TMS TM2 SIO0 SIO1 ADCR PM0 PM1 PM2 PM3 PM7 PM10 PM11 PM12 TCL0 TCL1 TCL2 TCL3 SCS TMC0 TMC1 TMC2 TOC0 TOC1
R/W
- -
Undefined
R
- -
00H
R/W
- -
- - - - - - - - - - - - - - - - - - - - -
Undefined
R R/W
-

1FH FFH
1FH FFH
R/W
- - - -
00H

88H 00H

User's Manual U11302EJ4V0UM
65
CHAPTER 3
CPU ARCHITECTURE
Table 3-3. Special-Function Register List (2/3)
Address Special-Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit
1 Bit 8 Bits 16 Bits
After Reset
FF60H FF61H FF62H FF63H FF68H FF69H FF6AH FF6BH FF80H FF84H FFA0H FFA1H FFA2H FFE0H FFE1H FFE4H FFE5H FFE8H FFE9H FFECH
Serial operating mode register 0 Serial bus interface control register Slave address register Interrupt timing specification register Serial operating mode register 1 Automatic data transmit/receive control register Automatic data transmit/receive address pointer Automatic data transmit/receive interval specification register A/D converter mode register A/D converter input select register Display mode register 0 Display mode register 1 Display mode register 2 Interrupt request flag register 0L Interrupt request flag register 0H Interrupt mask flag register 0L Interrupt mask flag register 0H Priority order specification flag register 0L Priority order specification flag register 0H External interrupt mode register
CSIM0 SBIC SVA SINT CSIM1 ADTC ADTP ADTI ADM ADIS DSPM0 DSPM1 DSPM2 xxxx IF0L IF0 xxxx IF0H MK0 x MK0L xxx MK0H PR0 PR0L
R/W

-

- - - - - - - - - - - - -
00H

Undefined 00H

-

- Note - -
01H 00H

-
FFH
xxxx PR0H INTM0
-
00H
Note
Only bit 7 can be manipulated, and only as a read operation.
66
User's Manual U11302EJ4V0UM
CHAPTER 3
CPU ARCHITECTURE
Table 3-3. Special-Function Register List (3/3)
Address Special-Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit
1 Bit 8 Bits 16 Bits
After Reset
Note Note
FFF0H FFF4H FFF7H FFF9H FFFAH FFFBH
Internal memory size switching register Internal expansion RAM size switching register Pull-up resistor option register Watchdog timer mode register Oscillation stabilization time select register Processor clock control register
IMS IXS PUO WDTM OSTS PCC
R/W W R/W
- -

- - - - - -

-
00H
04H
Note
The value after resetting the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS) depends on the product.
PD780204 PD780204A
CFH
PD780205
CAH
PD780205A
CFH
PD780206
CCH 0AH
PD780208
CFH
PD78P0208
CFH
IMS IXS
C8H None
When using the PD780204, 780205, 780206, and 780208, do not set any value other than that of IMS and IXS after reset. When using the PD780204A, 780205A, and 78P0208, the initial values of IMS are fixed to CFH, regardless of the internal memory capacity. Therefore, set the values shown below for each product before use.
PD780204A: C8H PD780205A: CAH PD78P0208: Value corresponding to mask ROM version
User's Manual U11302EJ4V0UM
67
CHAPTER 3
CPU ARCHITECTURE
3.3 Instruction Address Addressing
An instruction address is determined by program counter (PC) contents. The PC contents are normally
incremented (+1 for each byte) automatically according to the number of bytes of the instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and the program is branched by the following addressing (for details of instructions, refer to the 78K/0 Series Instructions User's Manual (U12326E)). 3.3.1 Relative addressing [Function] The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) and branched. The displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes a sign bit. In other words, the range of branch in relative addressing is between -128 and +127 of the start address of the following instruction. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed. [Illustration]
15 PC + 15 8 7 S jdisp8 15 PC 0 6 0 0 ... PC indicates the start address of the instruction after the BR instruction.
When S = 0, all bits of are 0. When S = 1, all bits of are 1.
68
User's Manual U11302EJ4V0UM
CHAPTER 3
CPU ARCHITECTURE
3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can branch to all the memory spaces. CALLF !addr11 instruction branches to the area from 0800H to 0FFFH. [Illustration] In the case of CALL !addr16 and BR !addr16 instructions
7 CALL or BR Low addr. High addr. 0
15 PC
87
0
In the case of CALLF !addr11 instruction
7 6 fa10-8 fa7-0 4 3 CALLF 0
15 PC 0 0 0 0
11 10 1
87
0
User's Manual U11302EJ4V0UM
69
CHAPTER 3
CPU ARCHITECTURE
3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can refer to the address stored in the memory table 40H to 7FH and branch to all the memory spaces. [Illustration]
7 Operation code 1
6 1
5 ta4
_0
1
0 1
15 Effective address 0 0 0 0 0 0 0
8 0
7 0
6 1
5
10 0
7
Memory (table) Low addr.
0
Effective address + 1
High addr.
15 PC
8
7
0
70
User's Manual U11302EJ4V0UM
CHAPTER 3
CPU ARCHITECTURE
3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration]
7 rp A
0
7 X
0
15 PC
8
7
0
User's Manual U11302EJ4V0UM
71
CHAPTER 3
CPU ARCHITECTURE
3.4 Operand Address Addressing
The following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register which functions as an accumulator (A and AX) in the general-purpose register area is automatically (implicitly) addressed. Of the PD780208 Subseries instruction words, the following instructions employ implied addressing.
Instruction MULU DIVUW ADJBA/ADJBS ROR4/ROL4 Register to Be Specified by Implied Addressing Register A for multiplicand and register AX for product storage Register AX for dividend and quotient storage Register A for storage of numeric values subject to decimal adjustment Register A for storage of digit data which undergoes digit rotation
[Operand format] Because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [Description example] In the case of MULU X With an 8-bit x 8-bit multiply instruction, the product of register A and register X is stored in AX. In this example, the A and AX registers are specified by implied addressing.
72
User's Manual U11302EJ4V0UM
CHAPTER 3
CPU ARCHITECTURE
3.4.2 Register addressing [Function] A general-purpose register is accessed as an operand. The general-purpose register to be accessed is specified by register bank select flags (RBS0 and RBS1) and the register specification code (Rn, RPn) in the operation code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [Operand format]
Identifier r rp Description X, A, C, B, E, D, L, H AX, BC, DE, HL
`r' and `rp' can be described using function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) as well as absolute names (R0 to R7 and RP0 to RP3). [Description example] MOV A, C; when selecting C register as r
Operation code
0
1
1
0
0
0
1
0
Register specification code
INCW DE; when selecting DE register pair as rp
Operation code
1
0
0
0
0
1
0
0
Register specification code
User's Manual U11302EJ4V0UM
73
CHAPTER 3
CPU ARCHITECTURE
3.4.3 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand format]
Identifier addr16 Description Label or 16-bit immediate data
[Description example] MOV A, !0FE00H; when setting !addr16 to FE00H
Operation code
1
0
0
0
1
1
1
0
Opcode
0
0
0
0
0
0
0
0
00H
1
1
1
1
1
1
1
0
FEH
[Illustration]
7 Opcode addr16 (lower) addr16 (lower)
0
Memory
74
User's Manual U11302EJ4V0UM
CHAPTER 3
CPU ARCHITECTURE
3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space to which this addressing is applied to is the 256-byte space from FE20H to FF1FH. An internal high-speed RAM and special-function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the total SFR area. In this area, ports which are frequently accessed in a program and compare and capture registers of the timer/event counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is set to 1. Refer to [Illustration] below. [Operand format]
Identifier saddr saddrp Description Label or immediate data indicating FE20H to FF1FH Label or immediate data indicating FE20H to FF1FH (even address only)
[Description example] MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H
Operation code
0
0
0
1
0
0
0
1
Opcode
0
0
1
1
0
0
0
0
30H (saddr-offset)
0
1
0
1
0
0
0
0
50H (immediate data)
[Illustration]
7 Opcode saddr-offset 0
15 Effective address 1 1 1 1 1 1 1
8
0
Short direct memory
When 8-bit immediate data is 20H to FFH, = 0 When 8-bit immediate data is 00H to 1FH, = 1
User's Manual U11302EJ4V0UM
75
CHAPTER 3
CPU ARCHITECTURE
3.4.5 Special-function register (SFR) addressing [Function] A memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing. [Operand format]
Identifier sfr sfrp Description Special-function register name 16-bit manipulatable special-function register name (even address only)
[Description example] MOV PM0, A; when selecting PM0 (FF20H) as sfr
Operation code
1
1
1
1
0
1
1
0
Opcode
0
0
1
0
0
0
0
0
20H (sfr-offset)
[Illustration]
7 Opcode sfr-offset
0
15 Effective address 1 1 1 1 1 1 1
87 1
0
SFR
76
User's Manual U11302EJ4V0UM
CHAPTER 3
CPU ARCHITECTURE
3.4.6 Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register bank select flag (RBS0 and RBS1) and the register pair specification code in the instruction code. This addressing can be carried out for all the memory spaces. [Operand format]
Identifier
--
Description [DE], [HL]
[Description example] MOV A, [DE]; when selecting [DE] as register pair
Operation code
1
0
0
0
0
1
0
1
[Illustration]
15 DE D
87 E
0
7 The contents of addressed memory are transferred 7 A 0
Memory
0
Memory address specified by register pair DE
User's Manual U11302EJ4V0UM
77
CHAPTER 3
CPU ARCHITECTURE
3.4.7 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. The HL register pair to be accessed is in the register bank specified with the register bank select flags (RBS0 and RBS1). Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format]
Identifier
--
Description [HL+byte]
[Description example] MOV A, [HL+10H]; When setting byte to 10H
Operation code
1
0
1
0
1
1
1
0
0
0
0
1
0
0
0
0
78
User's Manual U11302EJ4V0UM
CHAPTER 3
CPU ARCHITECTURE
3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. The HL, B, and C registers to be accessed are registers in the register bank specified with the register bank select flag (RBS0 and RBS1). Addition is performed by expanding the contents of the B or C register as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format]
Identifier
--
Description [HL+B], [HL+C]
[Description example] In the case of MOV A, [HL+B] (select B register)
Operation code
1
0
1
0
1
0
1
1
3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/reset upon generation of an interrupt request. Stack addressing can be used to address the internal high-speed RAM area only. [Description example] In the case of PUSH DE (save DE register)
Operation code
1
0
1
1
0
1
0
1
User's Manual U11302EJ4V0UM
79
CHAPTER 4
PORT FUNCTIONS
4.1 Port Functions
The PD780208 Subseries units incorporate two input ports, 16 output ports, and 56 I/O ports. Figure 4-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out various control operations. Besides port functions, the ports can also serve as on-chip hardware I/O pins. Figure 4-1. Port Types
P80
P00 Port 0
Port 8
P04 P10 P87 P90 Port 1
Port 9
P17 P20 P97 P100 Port 2
Port 10
P27 P30 P107 P110 Port 3
Port 11
P37 P70 P117 Port 7 P120 P74
Port 12
P127
80
User's Manual U11302EJ4V0UM
CHAPTER 4
PORT FUNCTIONS
Table 4-1. Port Functions (1/2)
Pin Name Function Alternate Function INTP0/TI0 INTP1 INTP2 INTP3 XT1 ANI0 to ANI7
P00 P01 P02 P03 P04 P10 to P17
Port 0. 5-bit I/O port.
Input only. Input/output can be specified in 1-bit units. If used as an input port, on-chip pull-up resistors can be used by software settings. Input only.
Port 1. 8-bit I/O port. Input/output can be specified in 1-bit units. If used as an input port, on-chip pull-up resistors can be used by software settings. Port 2. 8-bit I/O port. Input/output can be specified in 1-bit units. If used as an input port, on-chip pull-up resistors can be used by software settings.
P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P70 to P74
SI1 SO1 SCK1 STB BUSY SI0/SB0 SO0/SB1 SCK0
Port 3. 8-bit I/O port. Input/output can be specified in 1-bit units. LEDs can be driven directly. If used as an input port, on-chip pull-up resistors can be used by software settings. In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option.
TO0 TO1 TO2 TI1 TI2 PCL BUZ -
Port 7. N-ch open-drain 5-bit I/O port. Input/output can be specified in 1-bit units. LEDs can be driven directly. In mask ROM versions, use of pull-up resistors can be specified in 1-bit units with the mask option. Port 8. P-ch open-drain 8-bit high withstanding voltage output port. LEDs can be driven directly. In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option (can be specified as connected to VLOAD or VSS in 4-bit units). Port 9. P-ch open-drain 8-bit high withstanding voltage output port. LEDs can be driven directly. In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option (can be specified as connected to VLOAD or VSS in 4-bit units).
-
P80 to P87
FIP13 to FIP20
P90 to P97
FIP21 to FIP28
User's Manual U11302EJ4V0UM
81
CHAPTER 4
PORT FUNCTIONS
Table 4-1. Port Functions (2/2)
Pin Name Function Alternate Function FIP29 to FIP36
P100 to P107 Port 10. P-ch open-drain 8-bit high withstanding voltage I/O port. Input/output can be specified in 1-bit units. LEDs can be driven directly. In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option (can be specified as connected to VLOAD or VSS in 4-bit units). P110 to P117 Port 11. P-ch open-drain 8-bit high withstanding voltage I/O port. Input/output can be specified in 1-bit units. LEDs can be driven directly. In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option (can be specified as connected to VLOAD or VSS in 4-bit units). P120 to P127 Port 12. P-ch open-drain 8-bit high withstanding voltage I/O port. Input/output can be specified in 1-bit units. LEDs can be driven directly. In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option (can be specified as connected to VLOAD or VSS in 4-bit units).
FIP37 to FIP44
FIP45 to FIP52
82
User's Manual U11302EJ4V0UM
CHAPTER 4
PORT FUNCTIONS
4.2 Port Configuration
A port consists of the following hardware. Table 4-2. Port Configuration
Item Control registers Configuration Port mode register (PMm: m = 0, 1, 2, 3, 7, 10, 11, 12) Pull-up resistor option register (PUO) Total: 74 (2 input, 16 output, 56 I/O) * Mask ROM versions Total: 32 (software control: 27, mask option control: 5) * PD78P0208 ... Total: 27 * Mask ROM versions ... Total: 48 (mask option control: 48)
Ports Pull-up resistors
Pull-down resistors
4.2.1 Port 0 Port 0 is a 5-bit I/O port with an output latch. The P01 to P03 pins can be set to input mode/output mode in 1bit units using port mode register 0 (PM0). The P00 and P04 pins are input-only port pins. When the P01 to P03 pins are used as input port pins, on-chip pull-up resistors can be connected to them in 3-bit units using the pullup resistor option register (PUO). Alternate functions include external interrupt request input, external count clock input to the timer, and crystal connection for subsystem clock oscillation. RESET input sets port 0 to input mode. Figures 4-2 and 4-3 show block diagrams of port 0. Caution Because port 0 can also be used for external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. Thus, when the output mode is used, set the interrupt mask flag to 1.
User's Manual U11302EJ4V0UM
83
CHAPTER 4
PORT FUNCTIONS
Figure 4-2. Block Diagram of P00 and P04
RD
Internal bus
P00/INTP0/TI0, P04/XT1
Figure 4-3. Block Diagram of P01 to P03
VDD WRPUO PUO0 RD
P-ch
Selector
Internal bus
WRPORT Output latch (P01 to P03) P01/INTP1, P02/INTP2, P03/INTP3
WRPM PM01 to PM03
PUO: Pull-up resistor option register PM: RD: WR: Port mode register Port 0 read signal Port 0 write signal
84
User's Manual U11302EJ4V0UM
CHAPTER 4
PORT FUNCTIONS
4.2.2 Port 1 Port 1 is an 8-bit I/O port with an output latch. The P10 to P17 pins can be set to input mode/output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as input port pins, on-chip pullup resistors can be connected to them in 8-bit units using the pull-up resistor option register (PUO). Alternate functions include A/D converter analog input. RESET input sets port 1 to input mode. Figure 4-4 shows a block diagram of port 1. Caution A pull-up resistor cannot be connected to pins used for A/D converter analog input. Figure 4-4. Block Diagram of P10 to P17
VDD WRPUO PUO1 RD
P-ch
Selector
Internal bus
WRPORT Output latch (P10 to P17) P10/ANI0 to P17/ANI7
WRPM PM10 to PM17
PUO: Pull-up resistor option register PM: RD: WR: Port mode register Port 1 read signal Port 1 write signal
User's Manual U11302EJ4V0UM
85
CHAPTER 4
PORT FUNCTIONS
4.2.3 Port 2 Port 2 is an 8-bit I/O port with an output latch. The P20 to P27 pins can be set to input mode/output mode in 1-bit units using port mode register 2 (PM2). When the P20 to P27 pins are used as input port pins, on-chip pullup resistors can be connected to them in 8-bit units using the pull-up resistor option register (PUO). Alternate functions include serial interface data I/O, clock I/O, automatic transmit/receive busy input, and strobe output. RESET input sets port 2 to input mode. Figures 4-5 and 4-6 show block diagrams of port 2. Cautions 1. If used as serial interface pins, set the I/O and output latch according to each function. Refer to Figure 13-3 Format of Serial Operating Mode Register 0 and Figure 14-3 Format of Serial Operating Mode Register 1 for the settings. 2. When reading the pin state in SBI mode, set the PM2n bit of PM2 to 1 (n = 5, 6) (refer to the description of (10) Judging busy status of slave in 13.4.3 SBI mode operation). Figure 4-5. Block Diagram of P20, P21, P23 to P26
VDD WRPUO PUO2 RD
P-ch
Selector
Internal bus
WRPORT Output latch (P20, P21, P23 to P26) P20/SI1, P21/SO1, P23/STB, P24/BUSY, P25/SI0/SB0, P26/SO0/SB1
WRPM PM20, PM21, PM23 to PM26
Alternate function
PUO: Pull-up resistor option register PM: RD: WR: Port mode register Port 2 read signal Port 2 write signal
86
User's Manual U11302EJ4V0UM
CHAPTER 4
PORT FUNCTIONS
Figure 4-6. Block Diagram of P22 and P27
VDD WRPUO PUO2 RD
P-ch
Selector
Internal bus
WRPORT Output latch (P22, P27) P22/SCK1, P27/SCK0
WRPM PM22, PM27
Alternate function
PUO: Pull-up resistor option register PM: RD: WR: Port mode register Port 2 read signal Port 2 write signal
User's Manual U11302EJ4V0UM
87
CHAPTER 4
PORT FUNCTIONS
4.2.4 Port 3 Port 3 is an 8-bit I/O port with an output latch. The P30 to P37 pins can be set to input mode/output mode in 1-bit units using port mode register 3 (PM3). When the P30 to P37 pins are used as input port pins, on-chip pullup resistors can be connected to them in 8-bit units using the pull-up resistor option register (PUO). In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option. The
PD78P0208 does not contain pull-down resistors.
Port 3 can drive LEDs directly. Alternate functions include timer I/O, clock output, and buzzer output. RESET input sets port 3 to input mode. Figure 4-7 shows a block diagram of port 3. Figure 4-7. Block Diagram of P30 to P37
VDD WRPUO PUO3 RD
P-ch
Selector
Internal bus
WRPORT Output latch (P30 to P37)
P30/TO0 to P32/TO2, P33/TI1, P34/TI2, P35/PCL, P36/BUZ, P37
WRPM PM30 to PM37 Mask option Only mask ROM versions. The PD78P0208 has no pull-down resistors.
Alternate function
PUO: Pull-up resistor option register PM: RD: WR: Port mode register Port 3 read signal Port 3 write signal
88
User's Manual U11302EJ4V0UM
CHAPTER 4
PORT FUNCTIONS
4.2.5
Port 7
Port 7 is a 5-bit I/O port with an output latch. The P70 to P74 pins can be set to input mode/output mode in 1bit units using port mode register 7 (PM7). In mask ROM versions, use of pull-up resistors can be specified in 1bit units with the mask option. The PD78P0208 does not contain pull-up resistors. Port 7 can drive LEDs directly. RESET input sets port 7 to input mode. Figure 4-8 shows a block diagram of port 7. Caution The low-level input leak current flowing to the P70 to P74 pins varies depending on the following conditions. [For mask ROM version] * When a pull-up resistor is connected: * -3 A (max.) regardless of operational conditions * When a pull-up resistor is not connected: * -200 A (max.) during 1.5 clock cycles after read instruction execution to port 7 (P7) or port mode register 7 (PM7) * -3 A (max.) under other conditions [For PROM version] * -200 A (max.) during 1.5 clock cycles after read instruction execution to port 7 (P7) or port mode register 7 (PM7) * -3 A (max.) under other conditions Figure 4-8. Block Diagram of P70 to P74
VDD RD Mask option Only mask ROM versions. The PD78P0208 has no pull-up resistors.
Selector
Internal bus
WRPORT Output latch (P70 to P74) P70 to P74
WRPM PM70 to PM74
PM: Port mode register RD: Port 7 read signal WR: Port 7 write signal
User's Manual U11302EJ4V0UM
89
CHAPTER 4
PORT FUNCTIONS
4.2.6
Port 8
Port 8 is an 8-bit output-only port. In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option. Pull-down resistor connection to VLOAD or VSS can be specified in 4-bit units. The
PD78P0208 does not contain pull-down resistors.
Port 8 can drive LEDs directly. Alternate functions include VFD controller/driver display output. RESET input sets port 8 to output mode. Figure 4-9 shows a block diagram of port 8. Caution Adjust the number of pull-down resistors so that the total power dissipation (refer to 15.10 Calculating Total Power Dissipation) is not exceeded. Figure 4-9. Block Diagram of P80 to P87
Internal bus
WRPORT Output latch (P80 to P87) P-ch open-drain P80/FIP13 to P87/FIP20 VLOAD
Alternate function
Mask option Only mask ROM versions. The PD78P0208 has no pull-down resistors.
WR: Port 8 write signal
90
User's Manual U11302EJ4V0UM
CHAPTER 4
PORT FUNCTIONS
4.2.7
Port 9
Port 9 is an 8-bit output-only port. In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option. Pull-down resistor connection to VLOAD or VSS can be specified in 4-bit units. The
PD78P0208 does not contain pull-down resistors.
Port 9 can drive LEDs directly. Alternate functions include VFD controller/driver display output. RESET input sets port 9 to output mode. Figure 4-10 shows a block diagram of port 9. Caution Adjust the number of pull-down resistors so that the total power dissipation (refer to 15.10 Calculating Total Power Dissipation) is not exceeded. Figure 4-10. Block Diagram of P90 to P97
Internal bus
WRPORT Output latch (P90 to P97) P-ch open-drain P90/FIP21 to P97/FIP28 VLOAD
Alternate function
Mask option Only mask ROM versions. The PD78P0208 has no pull-down resistors.
WR: Port 9 write signal
User's Manual U11302EJ4V0UM
91
CHAPTER 4
PORT FUNCTIONS
4.2.8
Port 10
Port 10 is an 8-bit I/O port with an output latch. The P100 to P107 pins can be set to input mode/output mode in 1-bit units using port mode register 10 (PM10). In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option. Pull-down resistor connection to VLOAD or VSS can be specified in 4-bit units. The PD78P0208 does not contain pull-down resistors. Port 10 can drive LEDs directly. Alternate functions include VFD controller/driver display output. RESET input sets port 10 to input mode. Figure 4-11 shows a block diagram of port 10. Caution Adjust the number of pull-down resistors so that the total power dissipation (refer to 15.10 Calculating Total Power Dissipation) is not exceeded. Figure 4-11. Block Diagram of P100 to P107
RD
Selector
Internal bus
WRPORT Output latch (P100 to P107) P100/FIP29 to P107/FIP36
WRPM PM100 to PM107
VLOAD
Alternate function
Mask option Only mask ROM versions. The PD78P0208 has no pull-down resistors.
PM: Port mode register RD: Port 10 read signal WR: Port 10 write signal
92
User's Manual U11302EJ4V0UM
CHAPTER 4
PORT FUNCTIONS
4.2.9
Port 11
Port 11 is an 8-bit I/O port with an output latch. The P110 to P117 pins can be set to input mode/output mode in 1-bit units using port mode register 11 (PM11). In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option. Pull-down resistor connection to VLOAD or VSS can be specified in 4-bit units. The PD78P0208 does not contain pull-down resistors. Port 11 can drive LEDs directly. Alternate functions include VFD controller/driver display output. RESET input sets port 11 to input mode. Figure 4-12 shows a block diagram of port 11. Caution Adjust the number of pull-down resistors so that the total power dissipation (refer to 15.10 Calculating Total Power Dissipation) is not exceeded. Figure 4-12. Block Diagram of P110 to P117
RD
Selector
Internal bus
WRPORT Output latch (P110 to P117) P110/FIP37 to P117/FIP44
WRPM PM110 to PM117
VLOAD
Alternate function
Mask option Only mask ROM versions. The PD78P0208 has no pull-down resistors.
PM: Port mode register RD: Port 11 read signal WR: Port 11 write signal
User's Manual U11302EJ4V0UM
93
CHAPTER 4
PORT FUNCTIONS
4.2.10 Port 12 Port 12 is an 8-bit I/O port with an output latch. The P120 to P127 pins can be set to input mode/output mode in 1-bit units using port mode register 12 (PM12). In mask ROM versions, use of pull-down resistors can be specified in 1-bit units with the mask option. Pull-down resistor connection to VLOAD or VSS can be specified in 4-bit units. The PD78P0208 does not contain pull-down resistors. Port 12 can drive LEDs directly. Alternate functions include VFD controller/driver display output. RESET input sets port 12 to input mode. Figure 4-13 shows a block diagram of port 12. Caution Adjust the number of pull-down resistors so that the total power dissipation (refer to 15.10 Calculating Total Power Dissipation) is not exceeded. Figure 4-13. Block Diagram of P120 to P127
RD
Selector
Internal bus
WRPORT Output latch (P120 to P127) P120/FIP45 to P127/FIP52
WRPM
VLOAD PM120 to PM127 Mask option Only mask ROM versions. The PD78P0208 has no pull-down resistors.
Alternate function
PM: Port mode register RD: Port 12 read signal WR: Port 12 write signal
94
User's Manual U11302EJ4V0UM
CHAPTER 4
PORT FUNCTIONS
4.3 Port Function Control Registers
The following two types of registers control the ports. * Port mode registers (PM0, PM1, PM2, PM3, PM7, PM10, PM11, PM12) * Pull-up resistor option register (PUO) (1) Port mode registers (PM0, PM1, PM2, PM3, PM7, PM10, PM11, PM12) These registers are used to set port input/output in 1-bit units. PM0, PM1, PM2, PM3, PM7, PM10, PM11, and PM12 are independently set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM0 and PM7 to 1FH, and the other registers to FFH. When a port pin is used as an alternate-function pin, set the port mode register and the output latch according to Table 4-3. Cautions 1. Pins P00 and P04 are input-only pins. 2. Pins P80 to P87 and P90 to P97 are output-only pins. 3. As port 0 has an alternate function as external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. When the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand. Table 4-3. Port Mode Register and Output Latch Setting When Alternate Function Is Used
Pin Name Alternate Function Function Name P00 INTP0 TI0 P01, P02 P03 P04Note 1 P10 to P17 P30 to P32
Note 1
PMxx
Pxx
Pin Name
Alternate Function Function Name I/O Input Output Output Output Output Output
PMxx
Pxx
I/O Input Input Input Input Input Input Output 1 (fixed) 1 (fixed) 1 1 1 (fixed) 1 0 None None X X None X 0 P33, P34 P35 P36
TI1, TI2 PCL BUZ
1 0 0 0 0 0
X 0 0 0Note 2 0Note 2 0Note 2
INTP1, INTP2 INTP3 XT1 ANI0 to ANI7 TO0 to TO2
P100 to P107 FIP29 to FIP36 P110 to P117 FIP37 to FIP44 P120 to P127 FIP45 to FIP52
Notes 1. If a read instruction is executed to these ports in the alternate-function mode, the read data will be undefined. 2. Key scan data can be set while the VFD controller/driver is operating. Caution When port 2 is used as serial interface pins, I/O and the output latch should be set according to the function. For the settings, refer to Figure 13-3 Format of Serial Operating Mode Register 0 and Figure 14-3 Format of Serial Operating Mode Register 1. Remark X: Pxx: don't care Port output latch
PMxx: Port mode register
User's Manual U11302EJ4V0UM
95
CHAPTER 4
PORT FUNCTIONS
Figure 4-14. Format of Port Mode Register
Symbol PM0
7 0
6 0
5 0
4 1
3 PM03
2 PM02
1 PM01
0 1
Address FF20H
After reset 1FH
R/W R/W
PM1
PM17
PM16
PM15 PM14
PM13
PM12
PM11 PM10
FF21H
FFH
R/W
PM2
PM27
PM26
PM25 PM24
PM23
PM22
PM21 PM20
FF22H
FFH
R/W
PM3
PM37
PM36
PM35 PM34
PM33
PM32
PM31 PM30
FF23H
FFH
R/W
PM7
0
0
0
PM74
PM73
PM72
PM71 PM70
FF27H
1FH
R/W
PM10 PM107 PM106 PM105 PM104 PM103 PM102 PM101 PM100
FF2AH
FFH
R/W
PM11 PM117 PM116 PM115 PM114 PM113 PM112 PM111 PM110
FF2BH
FFH
R/W
PM12 PM127 PM126 PM125 PM124 PM123 PM122 PM121 PM120
FF2CH
FFH
R/W
PMmn 0 1
Pmn pin I/O mode selection (m = 0, 1, 2, 3, 7, 10, 11, 12 : n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off)
96
User's Manual U11302EJ4V0UM
CHAPTER 4
PORT FUNCTIONS
(2) Pull-up resistor option register (PUO) The PUO register enables or disables the on-chip pull-up resistor for each port pin. To enable the on-chip pullup resistor of a port pin, the pin must be in the input mode and the corresponding bit in the PUO register must be set to 1. For any pin specified as output mode or used as an analog input pin, the on-chip pull-up resistors cannot be used, regardless of the PUO register setting. PUO is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Cautions 1. The P00 and P04 pins do not incorporate a pull-up resistor. 2. When port 1 is used as analog input for the A/D converter, an on-chip pull-up resistor cannot be used even if 1 is set in PUO1. Figure 4-15. Format of Pull-up Resistor Option Register
Symbol PUO
7 0
6 0
5 0
4 0
<3>
<2>
<1>
<0>
Address FFF7H
After reset 00H
R/W R/W
PUO3 PUO2 PUO1 PUO0
PUOm 0 1
Pm on-chip pull-up resistor selection (m = 0, 1, 2, 3) On-chip pull-up resistor not used On-chip pull-up resistor used
User's Manual U11302EJ4V0UM
97
CHAPTER 4
PORT FUNCTIONS
4.4 Port Function Operations
Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again. (2) Input mode A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. Once data is written to the output latch, it is retained until data is written to the output latch again. Caution In the case of a 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed in 8-bit units. Therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined except for the manipulated bit. 4.4.2 Reading from I/O port (1) Output mode The output latch contents are read by a transfer instruction. The output latch contents do not change. (2) Input mode The pin status is read by a transfer instruction. The output latch contents do not change. 4.4.3 Operations on I/O port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again. (2) Input mode The output latch contents become undefined. However, the pin status does not change because the output buffer is turned off. Caution In the case of a 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed in 8-bit units. Therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined except for the manipulated bit.
98
User's Manual U11302EJ4V0UM
CHAPTER 4
PORT FUNCTIONS
4.5 Selection of Mask Option
The following mask option is provided in mask ROM versions. The PD78P0208 has no mask option. Table 4-4. Comparison Between Mask Option of Mask ROM Version and PD78P0208
Pin Name P30/TO0 to P32/TO2, P33/ TI1, P34/TI2, P35/PCL, P36/ BUZ, P37 P70 to P74 Mask Option of Mask ROM Version Can incorporate pull-down resistors in 1-bit units.
PD78P0208
Does not incorporate pull-down resistors.
Can incorporate pull-up resistors in 1-bit units. Can incorporate pull-down resistors in 1-bit units.
Does not incorporate pull-up resistors.
FIP0 to FIP12
Incorporates pull-down resistors (connected to VLOAD).
P80/FIP13 to P87/FIP20, P90/FIP21 to P97/FIP28, P100/FIP29 to P107/FIP36, P110/FIP37 to P117/FIP44, P120/FIP45 to P127/FIP52
Can incorporate pull-down resistors in Does not incorporate pull-down resistors. 1-bit units. The pull-down resistors can be specified to be connected to VLOAD or VSS in 4-bit units from P80.
User's Manual U11302EJ4V0UM
99
CHAPTER 5
CLOCK GENERATOR
5.1 Clock Generator Functions
The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This circuit oscillates at frequencies of 1 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register (PCC). (2) Subsystem clock oscillator The circuit oscillates at a frequency of 32.768 kHz. Oscillation cannot be stopped. If the subsystem clock oscillator is not used, the internal feedback resistor can be disabled by the processor clock control register (PCC). This decreases the power consumption in the STOP mode. The noise eliminator operates automatically to reduce the effect of switching noise during VFD display.
5.2 Clock Generator Configuration
The clock generator consists of the following hardware. Table 5-1. Clock Generator Configuration
Item Control registers Configuration Processor clock control register (PCC) Display mode register 0 (DSPM0) Display mode register 1 (DSPM1) Main system clock oscillator Subsystem clock oscillator
Oscillator
100
User's Manual U11302EJ4V0UM
CHAPTER 5
CLOCK GENERATOR
Figure 5-1. Clock Generator Block Diagram
FRC
XT1/P04 XT2
Subsystem clock oscillator
fXT
Clock output function
Selector
Noise eliminator fX/8 fX/16
Watch timer
Selector
DSPM06Note 1
DIGS0 to DIGS3Note 2
1/2
fX Watchdog timer X1 X2 Main system clock oscillator fX fX 2 Prescaler fX 22 fX 23 fX 24 fXT 2
Prescaler Clock to peripheral hardware
Selector
Standby controller
CPU clock (fCPU)
3
To INTP0 sampling clock
STOP MCC FRC CLS CSS PCC2 PCC1 PCC0
Processor clock control register
Internal bus
Notes 1. Bit 6 of display mode register 0 (DSPM0) 2. Bits 4 to 7 of display mode register 1 (DSPM1)
User's Manual U11302EJ4V0UM
101
CHAPTER 5
CLOCK GENERATOR
5.3 Clock Generator Control Registers
The clock generator is controlled by the following three registers. * Processor clock control register (PCC) * Display mode register 0 (DSPM0) * Display mode register 1 (DSPM1) (1) Processor clock control register (PCC) PCC sets CPU clock selection, the ratio of division, main system clock oscillator operation/stop, and subsystem clock oscillator internal feedback resistor enable/disable. PCC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PCC to 04H. Figure 5-2. Feedback Resistor of Subsystem Clock
FRC
P-ch
XT1
XT2
102
User's Manual U11302EJ4V0UM
CHAPTER 5
CLOCK GENERATOR
Figure 5-3. Format of Processor Clock Control Register
Symbol <7> PCC MCC
<6> FRC
<5> CLS
<4> CSS
3 0
2
1
0
Address FFFBH
After reset 04H
R/W R/WNote 1
PCC2 PCC1 PCC0 R/W
CSS 0
PCC2 PCC1 PCC0 0 0 0 0 1 0 0 1 1 0 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0
CPU clock (fCPU) selection fX fX/2 fX/2
2
fX/23 fX/2
4
1
0 0 0 0 1
fXT/2
Other than above R CLS 0 1 R/W FRC 0 1 R/W MCC 0 1 CPU clock status Main system clock Subsystem clock
Setting prohibited
Subsystem clock feedback resistor selection Internal feedback resistor used Internal feedback resistor not usedNote 2
Main system clock oscillation controlNote 3 Oscillation possible Oscillation stopped
Notes 1. Bit 5 is a read-only bit. 2. This bit can be set to 1 only when the subsystem clock is not used. 3. When the CPU is operating on the subsystem clock, MCC should be used to stop the main system clock oscillation. The STOP instruction should not be used. Cautions 1. Bit 3 must be set to 0. 2. Do not set MCC while an external clock is being input. This is because the X2 pin is pulled up to VDD. Remarks 1. fX: Main system clock oscillation frequency 2. fXT: Subsystem clock oscillation frequency
User's Manual U11302EJ4V0UM
103
CHAPTER 5
CLOCK GENERATOR
The fastest instruction of the PD780208 Subseries is executed in two CPU clocks. Therefore, the relationship between the CPU clock (fCPU) and minimum instruction execution time is as shown in Table 5-2. Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time
CPU Clock (fCPU) fX fX/2 fX/2 fX/2 fX/2
2 3 4
Minimum Instruction Execution Time: 2/fCPU 0.4 s 0.8 s 1.6 s 3.2 s 6.4 s 122 s
fXT/2
fX = 5.0 MHz, fXT = 32.768 kHz fX: Main system clock oscillation frequency fXT: Subsystem clock oscillation frequency (2) Display mode register 0 (DSPM0) This register sets the mode for the noise eliminator of the subsystem clock. DSPM0 is set with an 8-bit memory manipulation instruction. Only bit 7 (KSF) can be read with a 1-bit memory manipulation instruction. RESET input sets DSPM0 to 00H. Remark In addition to the function mentioned above, DSPM0 can also set the number of display segments/ total number of display outputs, display mode, and display key scan timing.
104
User's Manual U11302EJ4V0UM
CHAPTER 5
CLOCK GENERATOR
Figure 5-4. Format of Display Mode Register 0 (1/2)
Symbol DSPM0
7
6
5
4
3
2
1
0
Address FFA0H
After reset 00H
R/W R/W
KSF DSPM06 DSPM05 SEGS4 SEGS3 SEGS2 SEGS1 SEGS0
R/W SEGS4 SEGS3 SEGS2 SEGS1 SEGS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Display segment (display mode 1) 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Note 39 Note 40 Note
Display output total (display mode 2) 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Note
When the sum of digits and segments is over 53, specification of the number of digits has priority.
User's Manual U11302EJ4V0UM
105
CHAPTER 5
CLOCK GENERATOR
Figure 5-4. Format of Display Mode Register 0 (2/2)
Symbol DSPM0
7
6
5
4
3
2
1
0
Address FFA0H
After reset 00H
R/W R/WNote 1
KSF DSPM06 DSPM05 SEGS4 SEGS3 SEGS2 SEGS1 SEGS0
R/W DSPM05 Display mode setting 0 1 Display mode 1 (segment/character type) Display mode 2 (type in which a segment spans two or more grids)
R/W DSPM06 Mode of noise eliminator for subsystem clockNote 2 0 1 2.5 MHz < fX 5.0 MHz 1.25 MHz fX 2.5 MHzNote 3
R
KSF 0 1
Timing status Display timing Key scan timing
Notes 1. Bit 7 (KSF) is a read-only bit. 2. Set this bit according to the main system clock oscillation frequency (fX) selected. The noise eliminator operates during VFD display. 3. When fX is used between 1.25 MHz and 2.5 MHz, set bit 6 (DSPM06) to 1 prior to VFD display. Caution When the main system clock frequency selected is below 1.25 MHz and the VFD controller/ driver is enabled, make sure to use the main system clock for watch timer counting by setting TCL24 to 0.
106
User's Manual U11302EJ4V0UM
CHAPTER 5
CLOCK GENERATOR
(3) Display mode register 1 (DSPM1) Register to set display operation/stop. DSPM1 is set with an 8-bit memory manipulation instruction. RESET input sets DSPM1 to 00H. Remark In addition to setting display operation/stop, DSPM1 can also set the display digits/number of display patterns, cut width of the VFD output, and display cycle.
User's Manual U11302EJ4V0UM
107
CHAPTER 5
CLOCK GENERATOR
Figure 5-5. Format of Display Mode Register 1
Symbol
7
6
5
4
3
2
1
0
Address FFA1H
After reset 00H
R/W R/W
DSPM1 DIGS3 DIGS2 DIGS1 DIGS0 DIMS3 DIMS2 DIMS1 DIMS0
DIMS0 0 1
Display mode cycle setting 1024/fX is 1 display cycle (1 display cycle = 204.8 s: @ 5.0 MHz operation) 2048/fX is 1 display cycle (1 display cycle = 409.6 s: @ 5.0 MHz operation)
DIMS3 DIMS2 DIMS1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
VFD output signal cut width 1/16 2/16 4/16 6/16 8/16 10/16 12/16 14/16
DIGS3 DIGS2 DIGS1 DIGS0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Display digits (display mode 1) DSPM05 = 0 Display stopped (static display)Note 2 digits 3 digits 4 digits 5 digits 6 digits 7 digits 8 digits 9 digits 10 digits 11 digits 12 digits 13 digits 14 digits 15 digits 16 digits
Display patterns (display mode 2) DSPM05 = 1 Display stopped (static display)Note 2 patterns 3 patterns 4 patterns 5 patterns 6 patterns 7 patterns 8 patterns 9 patterns 10 patterns 11 patterns 12 patterns 13 patterns 14 patterns 15 patterns 16 patterns
Note
When setting display stopped, static display can be set by operating the port output latch.
Remarks 1. fX: Main system clock oscillation frequency 2. DSPM05: Bit 5 of display mode register 0 (DSPM0)
108
User's Manual U11302EJ4V0UM
CHAPTER 5
CLOCK GENERATOR
5.4 System Clock Oscillator
5.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin and its inverted signal to the X2 pin. Figure 5-6 shows an external circuit of the main system clock oscillator. Figure 5-6. External Circuit of Main System Clock Oscillator (a) Crystal or ceramic oscillation (b) External clock
IC X1
External clock
X1
X2 Crystal or ceramic resonator
X2
Caution Do not execute the STOP instruction or set bit 7 (MCC) of the processor clock control register (PCC) to 1 while an external clock is being input. This is because the operation of the main system clock is stopped and the X2 pin is pulled up to VDD if the STOP instruction is executed or MCC is set to 1.
User's Manual U11302EJ4V0UM
109
CHAPTER 5
CLOCK GENERATOR
5.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins. External clocks can be input to the subsystem clock oscillator. In this case, input a clock signal to the XT1 pin and its inverted signal to the XT2 pin. Figure 5-7 shows an external circuit of the subsystem clock oscillator. Figure 5-7. External Circuit of Subsystem Clock Oscillator (a) Crystal oscillation (b) External clock
32.768
XT1
External clock
XT1
kHz
XT2 IC
XT2
Cautions 1. When using the main system or subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in Figures 5-6 and 5-7 to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. When using the subsystem clock oscillator, pay special attention because the subsystem clock oscillator has low amplification to minimize power consumption. Figure 5-8 shows examples of incorrect resonator connection.
110
User's Manual U11302EJ4V0UM
CHAPTER 5
CLOCK GENERATOR
Figure 5-8. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring of connected circuit (b) Crossed signal lines
PORTn (n = 0 to 3, 7 to 12)
IC
X1
X2
IC
X1
X2
(c) High alternating current close to signal lines
(d) Current flowing through ground line of oscillator (potentials at points A, B, and C change)
VDD
IC
X1
X2 IC X1
Pmn X2
High current A B High current C
Remark When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Further, insert resistors in series on the side of XT2.
User's Manual U11302EJ4V0UM
111
CHAPTER 5
CLOCK GENERATOR
Figure 5-8. Examples of Incorrect Resonator Connection (2/2) (e) Signal fetched
IC
X1
X2
Remark When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Further, insert resistors in series on the side of XT2. Cautions 2. If XT2 and X1 are wired in parallel, malfunction may occur due to the crosstalk noise between XT2 and X1. To prevent this, connect the IC pin directly to the VSS pin located between the XT2 and X1 pins, and do not wire XT2 and X1 in parallel.
112
User's Manual U11302EJ4V0UM
CHAPTER 5
CLOCK GENERATOR
5.4.3 Divider The divider divides the main system clock oscillator output (fX) and generates various clocks. 5.4.4 When subsystem clock is not used If it is not necessary to use the subsystem clock for low power consumption operations and clock operations, connect the XT1 and XT2 pins as follows. XT1: Connect to VDD or VSS XT2: Leave open In this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator when the main system clock stops. To prevent this from happening, set bit 6 (FRC) of the processor clock control register (PCC) to disable use of the above internal feedback resistor. In this case also, connect the XT1 and XT2 pins as described above.
User's Manual U11302EJ4V0UM
113
CHAPTER 5
CLOCK GENERATOR
5.5 Clock Generator Operations
The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode. * Main system clock fX * Subsystem clock fXT * CPU clock fCPU * Clock to peripheral hardware The function and operation of the clock generator are determined by the processor clock control register (PCC) as follows. (a) Upon generation of the RESET signal, the lowest speed mode of the main system clock (6.4 s when operated at 5.0 MHz) is selected (PCC = 04H). Main system clock oscillation stops while a low level is applied to the RESET pin. (b) With the main system clock selected, one of the five stages of minimum instruction execution time (0.4 s, 0.8
s, 1.6 s, 3.2 s, and 6.4 s: when operated at 5.0 MHz) can be selected by setting PCC.
(c) With the main system clock selected, two standby modes, the STOP and HALT modes, are available. When the system is not using the subsystem clock, the power consumption in the STOP mode can be decreased if the internal feedback resistor is not used by setting bit 6 (FRC) of PCC. (d) PCC can be used to select the subsystem clock and to operate the system with low power consumption (122
s when operated at 32.768 kHz).
(e) With the subsystem clock selected, main system clock oscillation can be stopped using PCC. The HALT mode can be used, but the STOP mode cannot be used (subsystem clock oscillation cannot be stopped). (f) The main system clock is divided and supplied to the peripheral hardware. The subsystem clock is supplied to the watch timer and clock output functions only. Thus, the watch function and the clock output function can also be continued in the standby state. However, since all other peripheral hardware operate with the main system clock, the peripheral hardware also stop if the main system clock is stopped (except during operation using an externally input clock).
114
User's Manual U11302EJ4V0UM
CHAPTER 5
CLOCK GENERATOR
5.5.1 Main system clock operations During operation with the main system clock (when bit 5 (CLS) of the processor clock control register (PCC) is set to 0), the following operations are carried out via PCC settings. (a) Because the operation guaranteed instruction execution speed depends on the power supply voltage, the minimum instruction execution time can be changed by setting bits 0 to 2 (PCC0 to PCC2) of PCC. (b) If bit 7 (MCC) of PCC is set to 1 during operation with the main system clock, the main system clock oscillation does not stop. When bit 4 (CSS) of PCC is set to 1 and the operation is switched to subsystem clock operation (CLS = 1) after that, the main system clock oscillation stops (see Figure 5-9). Figure 5-9. Main System Clock Stop Function (1/2) (a) Operation when MCC is set after setting CSS during main system clock operation
MCC
CSS
CLS
Main system clock oscillation
Subsystem clock oscillation
CPU clock
(b) Operation when MCC is set during main system clock operation
MCC CSS CLS Main system clock oscillation "L" "L" Oscillation does not stop.
Subsystem clock oscillation
CPU clock
User's Manual U11302EJ4V0UM
115
CHAPTER 5
CLOCK GENERATOR
Figure 5-9. Main System Clock Stop Function (2/2) (c) Operation when CSS is set after setting MCC during main system clock operation
MCC
CSS
CLS Main system clock oscillation
Subsystem clock oscillation
CPU clock
5.5.2 Subsystem clock operations During operation with the subsystem clock (when bit 5 (CLS) of the processor clock control register (PCC) is set to 1), the following operations are carried out. (a) The minimum instruction execution time remains constant (122 s during operation at 32.768 kHz) irrespective of the setting of bits 0 to 2 (PCC0 to PCC2) of PCC. (b) Watchdog timer counting stops. Caution Do not execute the STOP instruction while the subsystem clock is operating.
116
User's Manual U11302EJ4V0UM
CHAPTER 5
CLOCK GENERATOR
5.6 Changing System Clock and CPU Clock Settings
5.6.1 Time required for switchover between system clock and CPU clock The system clock and CPU clock can be switched over by using bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC). The actual switchover operation is not performed directly after writing to the PCC; operation continues on the pre-switchover clock for several instructions (see Table 5-3). It can be judged by bit 5 (CLS) of PCC whether the system is operating on the main system clock or the subsystem clock. Table 5-3. Maximum Time Required for CPU Clock Switchover
Set Values Before Switchover CSS PCC2 PCC1 PCC0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1
Set Values After Switchover
CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0
x
x
x
0
0
0
16 instructions
16 instructions
16 instructions
16 instructions
fX/2fXT instructions (64 instructions) fX/4fXT instructions (32 instructions) fX/8fXT instructions (16 instructions) fX/16fXT instructions (8 instructions) fX/32fXT instructions (4 instructions)
0
0
1
8 instructions
8 instructions
8 instructions
8 instructions
0
0
1
0
4 instructions
4 instructions
4 instructions
4 instructions
0
1
1
2 instructions
2 instructions
2 instructions
2 instructions
1
0
0
1 instruction
1 instruction
1 instruction
1 instruction
1
x
x
x
1 instruction
1 instruction
1 instruction
1 instruction
1 instruction
Caution Selection of the CPU clock cycle division ratio (PCC0 to PCC2) and switchover from the main system clock to the subsystem clock (changing CSS from 0 to 1) should not be specified simultaneously. Simultaneous setting is possible, however, for selection of the CPU clock cycle division ratio (PCC0 to PCC2) and switchover from the subsystem clock to the main system clock (changing CSS from 1 to 0). Remarks 1. One instruction is the minimum instruction execution time with the pre-switchover CPU clock. 2. Figures in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz.
User's Manual U11302EJ4V0UM
117
CHAPTER 5
CLOCK GENERATOR
5.6.2 System clock and CPU clock switching procedure This section describes the procedure for switching between the system clock and CPU clock. Figure 5-10. System Clock and CPU Clock Switching
VDD
RESET
Interrupt request signal
System clock CPU clock
fX Minimum speed operation
fX Maximum speed operation
fXT Subsystem clock operation
fX High-speed operation
Wait (26.2 ms: @5.0 MHz) Internal reset operation
[1] The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released by setting the RESET signal to high level, the main system clock starts oscillating. At this time, the oscillation stabilization time (217/fX) is secured automatically. After that, the CPU starts executing the instruction at the minimum speed of the main system clock (6.4 s when operated at 5.0 MHz). [2] After the lapse of a sufficient time for the VDD voltage to increase to enable operation at maximum speeds, the processor clock control register (PCC) is rewritten and the maximum-speed operation is carried out. [3] Upon detection of a decrease of the VDD voltage due to an interrupt request signal, the main system clock is switched to the subsystem clock (which must be in an oscillation stable state). [4] Upon detection of VDD voltage reset due to an interrupt request signal, bit 7 (MCC) of PCC is set to 0 and oscillation of the main system clock is started. After the lapse of time required for stabilization of oscillation, PCC is rewritten and the maximum-speed operation is resumed. Caution When the main system clock is stopped and the subsystem clock is operating, switch to the main system clock after securing the oscillation stabilization time by program.
118
User's Manual U11302EJ4V0UM
CHAPTER 6
16-BIT TIMER/EVENT COUNTER
6.1 Outline of Timers Incorporated in PD780208 Subseries
This chapter explains the 16-bit timer/event counter. First of all, the timers incorporated in the PD780208 Subseries and other related parts are outlined below. (1) 16-bit timer/event counter (TM0) The TM0 can be used for an interval timer, PWM output, pulse width measurement (infrared remote control receive function), external event counter or square-wave output of any frequency. (2) 8-bit timer/event counters (TM1 and TM2) TM1 and TM2 can be used for an interval timer and an external event counter and to output square waves with any selected frequency. Two 8-bit timer/event counters can be used as one 16-bit timer/event counter (refer to CHAPTER 7 8-BIT TIMER/EVENT COUNTER). (3) Watch timer (TM3) This timer can set a flag every 0.5 seconds and simultaneously generate interrupt requests at preset time intervals (refer to CHAPTER 8 WATCH TIMER). (4) Watchdog timer (WDTM) WDTM can perform a watchdog timer function or generate non-maskable interrupt requests, maskable interrupt requests and RESET at preset time intervals (refer to CHAPTER 9 WATCHDOG TIMER). (5) Clock output controller This circuit supplies other devices with the divided main system clock and the subsystem clock (refer to CHAPTER 10 CLOCK OUTPUT CONTROLLER). (6) Buzzer output controller This circuit outputs the buzzer frequency obtained by dividing the main system clock (refer to CHAPTER 11 BUZZER OUTPUT CONTROLLER).
User's Manual U11302EJ4V0UM
119
CHAPTER 6
16-BIT TIMER/EVENT COUNTER
Table 6-1. Timer/Event Counter Operations
16-Bit Timer/ Event Counter Operation mode Function Interval timer External event counter Timer output PWM output Pulse width measurement Square-wave output Interrupt request Test input 1 channel - 8-Bit Timer/ Event Counter 2 channels - - - Watch Timer 1 channel - - - - - -
Note 1
Watchdog Timer 1 channelNote 2 - - - - - -
Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time. 2. The watchdog timer can perform either the watchdog timer function or the interval timer function.
6.2 16-Bit Timer/Event Counter Functions
The 16-bit timer/event counter (TM0) has the following functions. * Interval timer * PWM output * Pulse width measurement * External event counter * Square-wave output
120
User's Manual U11302EJ4V0UM
CHAPTER 6
16-BIT TIMER/EVENT COUNTER
(1) Interval timer TM0 generates interrupt requests at the preset time interval. Table 6-2. 16-Bit Timer/Event Counter Interval Time
Minimum Interval Time 2 x TI0 input cycle 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) Maximum Interval Time 216 x TI0 input cycle 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 219 x 1/fX (104.9 ms) Resolution TI0 input edge cycle 1/fX (200 ns) 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s)
Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 5.0 MHz. (2) PWM output TM0 can generate 14-bit resolution PWM output. (3) Pulse width measurement TM0 can measure the pulse width of an externally input signal. (4) External event counter TM0 can measure the number of pulses of an externally input signal. (5) Square-wave output TM0 can output a square wave with any selected frequency. Table 6-3. 16-Bit Timer/Event Counter Square-Wave Output Ranges
Minimum Pulse Width 2 x TI0 input cycle 2 x 1/fX (400 ns) 22 23 x 1/fX (800 ns) x 1/fX (1.6 s) Maximum Pulse Width 216 216 217 218 x TI0 input cycle x 1/fX (13.1 ms) x 1/fX (26.2 ms) x 1/fX (52.4 ms) Resolution TI0 input edge cycle 1/fX (200 ns) 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s)
24 x 1/fX (3.2 s)
219 x 1/fX (104.9 ms)
Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 5.0 MHz.
User's Manual U11302EJ4V0UM
121
CHAPTER 6
16-BIT TIMER/EVENT COUNTER
6.3 16-Bit Timer/Event Counter Configuration
The 16-bit timer/event counter consists of the following hardware. Table 6-4. 16-Bit Timer/Event Counter Configuration
Item Timer register Registers 16 bits x 1 (TM0) 16-bit compare register: 16-bit capture register: 1 (TO0) Timer clock select register 0 (TCL0) 16-bit timer mode control register (TMC0) 16-bit timer output control register (TOC0) Port mode register 3 (PM3) External interrupt mode register (INTM0) Sampling clock select register (SCS)Note 1 (CR00) 1 (CR01) Configuration
Timer outputs Control registers
Note
Refer to Figure 16-1 Basic Configuration of Interrupt Function.
122
User's Manual U11302EJ4V0UM
Figure 6-1. Block Diagram of 16-Bit Timer/Event Counter (Timer Mode)
Internal bus
0 16-bit compare register (CR00)
15
Match
Match INTTM0 Note 2 16-bit timer/event counter output controller
CHAPTER 6
User's Manual U11302EJ4V0UM
Selector
fX fX/2 2 fX/2 fX/23 TI0/P00/INTP0
Note 1
TO0/P30
0 16-bit timer register lower 8 bits (TM0L)
7 16-bit timer register higher 8 bits (TM0H) Clear
15
16-BIT TIMER/EVENT COUNTER
OVF
3
2
Clear
Selector
3 INTP0 0
TCL06 TCL05 TCL04
15 16-bit capture register (CR01)
TMC03 TMC02 TMC01 OVF0
LVS0 LVR0 TOC01 TOE0 16-bit timer output control register
Timer clock select register 0
16-bit timer mode control register
Internal bus
Notes 1. Edge detector 2. For the configuration of the 16-bit timer/event counter output controller, refer to Figure 6-3.
123
fX/2 fX/22 fX/2
User's Manual U11302EJ4V0UM
3
Selector
Selector
124
fX 3
TCL06 TCL05 TCL04
Figure 6-2. Block Diagram of 16-Bit Timer/Event Counter (PWM Mode)
Internal bus
16-bit compare register (CR00)
CHAPTER 6
PWM pulse generator
TO0/P30
16-BIT TIMER/EVENT COUNTER
16-bit timer register (TM0)
16-bit capture register (CR01)
TOC01 TOE0
Timer clock select register 0
P30 output latch
PM30 Port mode register 3
16-bit timer output control register Internal bus
Remark The circuitry enclosed by the dotted line is the output controller.
Figure 6-3. Block Diagram of 16-Bit Timer/Event Counter Output Controller
Level F/F (LV0) LVR0 R
LVS0 TOC01
S INV
Selector
Q
TO0/P30
CHAPTER 6
Selector
P30 output latch 3
PM30Note 2
User's Manual U11302EJ4V0UM
INTTM0 TI0/P00/INTP0 Edge detector
16-BIT TIMER/EVENT COUNTER
3 PWM pulse generator 2 ES10, ES11Note 1 Active level control
TMC01 to TMC03
TOC01
TMC01 TOE0 to TMC03
Notes 1. Bits 2 and 3 of the external interrupt mode register (INTM0) 2. Bit 0 of port mode register 3 (PM3) Remark The circuitry enclosed by the dotted line is the output controller.
125
CHAPTER 6
16-BIT TIMER/EVENT COUNTER
(1) 16-bit compare register (CR00) CR00 is a 16-bit register whose value is constantly compared with the 16-bit timer register (TM0) count value, and an interrupt request (INTTM0) is generated if they match. It can also be used as the register that holds the interval time when TM0 is set to interval timer operation, and as the register that sets the pulse width when TM0 is set to PWM output operation. CR00 is set with a 16-bit memory manipulation instruction. Values from 0001H to FFFFH can be set. RESET input makes CR00 undefined. Cautions 1. The PWM data (14 bits) must be set in the higher 14 bits of CR00. The lower two bits must be set to 00. 2. CR00 should be set to a value other than 0000H. This means that when the timer is used as an event counter, a 1-pulse count operation is not possible. 3. When the value after CR00 is changed is smaller than that of the 16-bit timer register (TM0), TM0 continues to count and overflows, then resumes counting from 0. Therefore, if the value after CR00 is changed is smaller than the value before CR00 is changed, the timer needs to be restarted after CR00 is changed. (2) 16-bit capture register (CR01) CR01 is a 16-bit register used to capture the contents of the 16-bit timer (TM0). The capture trigger is the INTP0/TI0 pin valid edge input. The INTP0 valid edge is set by the external interrupt mode register (INTM0). CR01 is read with a 16-bit memory manipulation instruction. RESET input makes CR01 undefined. Caution If the valid edge for the TI0/P00 pin is input during a read from CR01, CR01 does not perform the capture operation and holds the previous data. In this case, however, the interrupt request flag (PIF0) is set because a valid edge is detected. (3) 16-bit timer register (TM0) TM0 is a 16-bit register that counts the count pulse. TM0 is read with a 16-bit memory manipulation instruction. RESET input sets TM0 to 0000H. Caution As reading of the value of TM0 is performed via CR01, the previously set value of CR01 is lost.
126
User's Manual U11302EJ4V0UM
CHAPTER 6
16-BIT TIMER/EVENT COUNTER
6.4 16-Bit Timer/Event Counter Control Registers
The following six registers are used to control the 16-bit timer/event counter. * Timer clock select register 0 (TCL0) * 16-bit timer mode control register (TMC0) * 16-bit timer output control register (TOC0) * Port mode register 3 (PM3) * External interrupt mode register (INTM0) * Sampling clock select register (SCS) (1) Timer clock select register 0 (TCL0) This register is used to set the count clock of the 16-bit timer register. TCL0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TCL0 to 00H. Remark TCL0 has the function of setting the PCL output clock in addition to that of setting the count clock of the 16-bit timer register.
User's Manual U11302EJ4V0UM
127
CHAPTER 6
16-BIT TIMER/EVENT COUNTER
Figure 6-4. Format of Timer Clock Select Register 0
Symbol <7> TCL0
6
5
4
3
2
1
0
Address FF40H
After reset 00H
R/W R/W
CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00
TCL03 TCL02 TCL01 TCL00 PCL output clock selection 0 0 1 1 1 1 1 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 1 0 1 0 1 0 fXT (32.768 kHz) fX/23 (625 kHz)
4 fX/2 (313 kHz) 5
fX/2 (156 kHz)
6 fX/2 (78.1 kHz) 7 fX/2 (39.1 kHz)
fX/28 (19.5 kHz) Setting prohibited
Other than above
16-bit timer register count clock TCL06 TCL05 TCL04 selection 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 TI0 (Valid edge specifiable) fX (5.0 MHz) fX/2 (2.5 MHz)
2 fX/2 (1.25 MHz) 3 fX/2 (625 kHz)
Other than above
Setting prohibited
CLOE 0 1
PCL output control Output disabled Output enabled
Cautions 1. The TI0/INTP0 pin valid edge is specified by the external interrupt mode register (INTM0), and the sampling clock frequency is selected by the sampling clock select register (SCS). 2. When enabling PCL output, set TCL00 to TCL03, then set CLOE to 1 with a 1-bit memory manipulation instruction. 3. To read the count value when TI0 has been specified as the TM0 count clock, the value should be read from TM0, not from the 16-bit capture register (CR01). 4. If TCL0 is to be rewritten with data other than identical data, the timer operation must be stopped first. Remarks 1. fX: Main system clock oscillation frequency 2. fXT: Subsystem clock oscillation frequency 3. TI0: 16-bit timer/event counter input pin 4. TM0: 16-bit timer register 5. Figures in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz. 6. Refer to CHAPTER 10 CLOCK OUTPUT CONTROLLER for PCL.
128
User's Manual U11302EJ4V0UM
CHAPTER 6
16-BIT TIMER/EVENT COUNTER
(2) 16-bit timer mode control register (TMC0) This register sets the 16-bit timer operating mode, the 16-bit timer register clear mode and output timing, and detects an overflow. TMC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC0 to 00H. Caution The 16-bit timer register starts operating when TMC01 to TMC03 are set to a value other than 0, 0, 0 (operation stop mode). To stop the timer operation, set TMC01 to TCM03 to 0, 0, 0.
User's Manual U11302EJ4V0UM
129
CHAPTER 6
16-BIT TIMER/EVENT COUNTER
Figure 6-5. Format of 16-Bit Timer Mode Control Register
Symbol TMC0 7 0 6 0 5 0 4 0 3 2 1 <0> Address FF48H After reset 00H R/W R/W
TMC03 TMC02 TMC01 OVF0
OVF0 0 1
16-bit timer register overflow detection Overflow not detected Overflow detected Operating mode & clear mode selection Operation stop (TM0 cleared to 0) PWM mode (free-running) Free-running mode TO0 output timing selection No change Interrupt request generation Not generated
TMC03 TMC02 TMC01
0
0
0
0
0
1
PWM pulse output
Generated on match between TM0 and CR00
0 0
1 1
0 1
Match between TM0 and CR00 Match between TM0 and CR00 or TI0 valid edge
1
0
0
Clear & start on TI0 valid edge
Match between TM0 and CR00 Match between TM0 and CR00 or TI0 valid edge
1
0
1 Clear & start on match between TM0 and CR00
1 1
1 1
0 1
Match between TM0 and CR00 Match between TM0 and CR00 or TI0 valid edge
Cautions 1. Switch the clear mode and the TO0 output timing after stopping the timer operation (by setting TMC01 to TMC03 to 0, 0, 0). 2. The valid edge of the TI0/INTP0 pin is specified by the external interrupt mode register (INTM0) and the sampling clock frequency is selected by the sampling clock select register (SCS). 3. When using the PWM mode, set the PWM mode and then set data to CR00. Remark TO0: TI0: TM0: 16-bit timer/event counter output pin 16-bit timer/event counter input pin 16-bit timer register
CR00: Compare register 00
130
User's Manual U11302EJ4V0UM
CHAPTER 6
16-BIT TIMER/EVENT COUNTER
(3) 16-bit timer output control register (TOC0) This register controls the operation of the 16-bit timer/event counter output controller. It sets/resets the R-S type flip-flop (LV0), sets the active level in PWM mode, and enables/disables inversion in modes other than PWM mode and data output mode. TOC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TOC0 to 00H. Figure 6-6. Format of 16-Bit Timer Output Control Register
Symbol TOC0
7 0
6 0
5 0
4 0
<3> LVS0
<2>
1
<0>
Address FF4EH
After reset 00H
R/W R/W
LVR0 TOC01 TOE0
TOE0 0 1
16-bit timer/event counter output control Output disabled (port mode) Output enabled
In PWM mode TOC01 0 1 Active level selection Active high Active low
In other modes Timer output F/F control Inversion operation disabled Inversion operation enabled
LVS0 0 0 1 1
LVR0 0 1 0 1
16-bit timer/event counter timer output F/F status setting No change Timer output F/F reset (0) Timer output F/F set (1) Setting prohibited
Cautions 1. Timer operation must be stopped before setting TOC0. 2. If LVS0 and LVR0 are read after data is set, they will be 0.
User's Manual U11302EJ4V0UM
131
CHAPTER 6
16-BIT TIMER/EVENT COUNTER
(4) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P30/TO0 pin for timer output, set PM30 and the output latch of P30 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH. Figure 6-7. Format of Port Mode Register 3
Symbol PM3
7
6
5
4
3
2
1
0
Address FF23H
After reset FFH
R/W R/W
PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
PM3n 0 1
P3n pin I/O mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off)
132
User's Manual U11302EJ4V0UM
CHAPTER 6
16-BIT TIMER/EVENT COUNTER
(5) External interrupt mode register (INTM0) This register is used to set the INTP0 to INTP2 and TI0 valid edges. INTM0 is set with an 8-bit memory manipulation instruction. RESET input sets INTM0 to 00H. Remarks 1. The INTP0 pin is also used as TI0/P00. 2. The valid edge of INTP3 is fixed to the falling edge. Figure 6-8. Format of External Interrupt Mode Register
Symbol
7
6
5
4
3
2
1 0
0 0
Address FFECH
After reset 00H
R/W R/W
INTM0 ES31 ES30 ES21 ES20 ES11 ES10
ES11 ES10 INTP0/TI0 valid edge selection 0 0 1 1 0 1 0 1 Falling edge Rising edge Setting prohibited Both falling and rising edges
ES21 ES20 INTP1 valid edge selection 0 0 1 1 0 1 0 1 Falling edge Rising edge Setting prohibited Both falling and rising edges
ES31 ES30 INTP2 valid edge selection 0 0 1 1 0 1 0 1 Falling edge Rising edge Setting prohibited Both falling and rising edges
Caution When using the INTP0/TI0/P00 pin as a timer input pin (TI0), stop the operation of the 16-bit timer by clearing bits 1 to 3 (TMC01 to TMC03) of the 16-bit timer mode control register (TMC0) to 0, 0, 0, before setting the valid edge of TI0. When using the INTP0/TI0/P00 pin as an external interrupt input pin (INTP0), the valid edge of INTP0 may be set while the 16-bit timer is operating.
User's Manual U11302EJ4V0UM
133
CHAPTER 6
16-BIT TIMER/EVENT COUNTER
(6) Sampling clock select register (SCS) This register sets the clock to be used for sampling the valid edge input to INTP0. When remote controlled reception is carried out using INTP0, digital noise is eliminated using the sampling clock. SCS is set with an 8-bit memory manipulation instruction. RESET input sets SCS to 00H. Figure 6-9. Format of Sampling Clock Select Register
Symbol SCS
7 0
6 0
5 0
4 0
3 0
2 0
1
0
Address FF47H
After reset 00H
R/W R/W
SCS1 SCS0
SCS1 SCS0 INTP0 sampling clock selection 0 0 1 1 0 1 0 1 fX/2N+1 Setting prohibited
6 fX/2 (78.1 kHz) 7 fX/2 (39.1 kHz)
Caution fX/2N+1 is the clock supplied to the CPU, and fX/26 and fX/27 are clocks supplied to peripheral hardware. fX/2N+1 is stopped in HALT mode. Remarks 1. N: Value set in bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC) (N = 0 to 4) 2. fX: Main system clock oscillation frequency 3. Figures in parentheses apply to operation with fX = 5.0 MHz.
134
User's Manual U11302EJ4V0UM
CHAPTER 6
16-BIT TIMER/EVENT COUNTER
6.5 16-Bit Timer/Event Counter Operations
6.5.1 Interval timer operations By setting bits 2 and 3 (TMC02 and TMC03) of the 16-bit timer mode control register (TMC0) to 1, 1, the 16-bit timer/event counter operates as an interval timer. Interrupt requests are generated repeatedly using the count value set in the 16-bit compare register (CR00) beforehand as the interval. When the count value of the 16-bit timer register (TM0) matches the value set to CR00, counting continues with the TM0 value cleared to 0 and the interrupt request signal (INTTM0) is generated. CR00 should be set to a value other than 0000H. The count clock of the 16-bit timer/event counter can be selected using bits 4 to 6 (TCL04 to TCL06) of timer clock select register 0 (TCL0). For the operation when the value of the compare register is changed during timer count operation, refer to 6.6 16Bit Timer/Event Counter Operating Precautions (3). Figure 6-10. Interval Timer Configuration Diagram
16-bit compare register (CR00)
INTTM0 fX fX/2 fX/2
2 3
Selector
fX/2
16-bit timer register (TM0)
OVF0
TI0/P00/INTP0 Clear circuit
User's Manual U11302EJ4V0UM
135
CHAPTER 6
16-BIT TIMER/EVENT COUNTER
Figure 6-11. Interval Timer Operation Timing
t
Count clock
TM0 count value
0000 0001 Count start
N
0000 Clear N
0001
N
0000 Clear N
0001
N
CR00
N
N
INTTM0 Interrupt request acknowledgment Interrupt request acknowledgment TO0
Interval time
Interval time
Interval time
Remark Interval time = (N + 1) x t: N = 0001H to FFFFH Table 6-5. 16-Bit Timer/Event Counter Interval Time
TCL06 TCL05 TCL04 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Minimum Interval Time 2 x TI0 input cycle 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) Setting prohibited Maximum Interval Time 216 x TI0 input cycle 216 x 1/fX (13.1 ms) Resolution TI0 input edge cycle 1/fX (200 ns) 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s)
217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 219 x 1/fX (104.9 ms)
Other than above
Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 5.0 MHz.
136
User's Manual U11302EJ4V0UM
CHAPTER 6
16-BIT TIMER/EVENT COUNTER
6.5.2 PWM output operations By setting bits 1 to 3 (TMC01 to TMC03) of the 16-bit timer mode control register (TMC0) to 1, 0, 0, the 16-bit timer/ event counter operates as PWM output. Pulses with a duty determined by the value set in the 16-bit compare register (CR00) beforehand are output from the TO0/P30 pin. Set the active level width of the PWM pulse to the higher 14 bits of CR00. Select the active level using bit 1 (TOC01) of the 16-bit timer output control register (TOC0). This PWM pulse has a 14-bit resolution. The pulse can be converted to an analog voltage by integrating it with an external low-pass filter (LPF). The PWM pulse has a combination of the basic cycle determined by 28/ and the sub-cycle determined by 214/ so that the time constant of the external LPF can be shortened. Count clock can be selected using bits 4 to 6 (TCL04 to TCL06) of timer clock select register 0 (TCL0). PWM output enable/disable can be selected using bit 0 (TOE0) of TOC0. Cautions 1. CR00 should be set after selecting the PWM operation mode. 2. Be sure to write 0 to bits 0 and 1 of CR00. 3. Do not select the PWM operation mode when an external clock is input from the TI0/P00 pin. By integrating 14-bit resolution PWM pulses with an external low-pass filter, they can be converted to an analog voltage and used for electronic tuning and D/A converter applications, etc. The analog output voltage (VAN) used for D/A conversion with the configuration shown in Figure 6-12 is as follows. VAN = VREF x Compare register (CR00) value 216 VREF: External switching circuit reference voltage Figure 6-12. Example of D/A Converter Configuration with PWM Output
PD780205
VREF PWM signal TO0/P30
Switching circuit
Analog output (VAN) Low-pass filter
User's Manual U11302EJ4V0UM
137
CHAPTER 6
16-BIT TIMER/EVENT COUNTER
Figure 6-13 shows an example in which PWM output is converted to an analog voltage and used in a voltage synthesizer type TV tuner. Figure 6-13. TV Tuner Application Circuit Example
+110 V
PD780205
22 k 47 k 100 pF 0.22 F TO0/P30 8.2 k 8.2 k 0.22 F 0.22 F Electronic tuner 47 k 47 k
VSS
GND
6.5.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI0/P00 pin using the 16-bit timer register (TM0). There are two measurement methods: measuring with the 16-bit timer register (TM0) used in free-running mode, and measuring by restarting the timer in synchronization with the valid edge of the signal input to the TI0/P00 pin. (1) Pulse width measurement in free-running mode When the 16-bit timer register (TM0) is operated in free-running mode, if the edge specified by the external interrupt mode register (INTM0) is input, the value of TM0 is taken into the capture register (CR01) and an external interrupt request signal (INTP0) is set. Any of three edge specifications can be selected--rising, falling, or both edges--by using bits 2 and 3 (ES10 and ES11) of INTM0. For valid edge detection, sampling is performed at the interval selected by the sampling clock select register (SCS), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width.
138
User's Manual U11302EJ4V0UM
CHAPTER 6
16-BIT TIMER/EVENT COUNTER
Figure 6-14. Configuration Diagram for Pulse Width Measurement in Free-Running Mode
fX fX/2 fX/22 fX/23 Selector 16-bit timer register (TM0) OVF0
TI0/P00/INTP0
16-bit capture register (CR01) INTP0
Internal bus
Figure 6-15. Timing of Pulse Width Measurement Operation in Free-Running Mode (with Both Edges Specified)
t
Count clock
TM0 count value
0000 0001
D0
D1
FFFF 0000
D2
D3
TI0 pin input
CR01 captured value
D0
D1
D2
D3
INTP0
OVF0
(D1 _ D0) x t
(10000H _ D1 + D2) x t
(D3 _ D2) x t
User's Manual U11302EJ4V0UM
139
CHAPTER 6
16-BIT TIMER/EVENT COUNTER
(2) Pulse width measurement by means of restart When input of a valid edge to the TI0/P00 pin is detected, the count value of the 16-bit timer register (TM0) is taken into the 16-bit capture register (CR01), and then the pulse width of the signal input to the TI0/P00 pin is measured by clearing TM0 and restarting the count. The edge specification can be selected from three types--rising, falling, and both edges--by using bits 2 and 3 (ES10 and ES11) of the external interrupt mode register (INTM0). For valid edge detection, sampling is performed at the interval selected by the sampling clock select register (SCS), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. Figure 6-16. Timing of Pulse Width Measurement Operation by Means of Restart (with Both Edges Specified)
t
Count clock
TM0 count value
0000 0001
D0
0000
0001
D1
0000
0001
TI0 pin input
CR01 captured value
D0
D1
INTP0
(D0 + 1) x t
(D1 + 1) x t
6.5.4 External event counter operation The external event counter counts the number of external clock pulses input to the TI0/P00 pin using the 16-bit timer register (TM0). TM0 is incremented each time the valid edge specified by the external interrupt mode register (INTM0) is input. When the TM0 count value matches the 16-bit compare register (CR00) value, TM0 is cleared to 0 and the interrupt request signal (INTTM0) is generated. Set CR00 to a value other than 0000H (a 1-pulse count operation cannot be performed). The rising edge, falling edge or both edges can be selected using bits 2 and 3 (ES10 and ES11) of INTM0. For valid edge detection, sampling is performed at the interval selected by the sampling clock select register (SCS), and a counter operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width.
140
User's Manual U11302EJ4V0UM
CHAPTER 6
16-BIT TIMER/EVENT COUNTER
Figure 6-17. External Event Counter Configuration Diagram
16-bit compare register (CR00)
Clear
INTTM0
TI0 valid edge
16-bit timer register (TM0)
OVF0
INTP0 16-bit capture register (CR01)
Internal bus
Figure 6-18. External Event Counter Operation Timing (with Rising Edge Specified)
TI0 pin input
TM0 count value
0000 0001
0002 0003 0004 0005
N_1
N
0000 0001 0002 0003
CR00
N
INTTM0
User's Manual U11302EJ4V0UM
141
CHAPTER 6
16-BIT TIMER/EVENT COUNTER
6.5.5 Square-wave output operation The 16-bit timer/event counter outputs a square-wave of any frequency with the value preset to the 16-bit compare register (CR00) as the interval. The TO0/P30 pin output status is reversed at intervals of the count value preset to CR00 by setting bit 0 (TOE0) and bit 1 (TOC01) of the 16-bit timer output control register (TOC0) to 1. This enables a square wave with any selected frequency to be output. Table 6-6. 16-Bit Timer/Event Counter Square-Wave Output Ranges
TCL06 TCL05 TCL04 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Minimum Pulse Width 2 x TI0 input cycle 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) Maximum Pulse Width 216 x TI0 input cycle 216 x 1/fX (13.1 ms) Resolution TI0 input edge cycle 1/fX (200 ns) 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s)
217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 219 x 1/fX (104.9 ms)
Remarks 1. fX: Main system clock oscillation frequency 2. TCL04 to TCL06: Bits 4 to 6 of timer clock select register 0 (TCL0) 3. Figures in parentheses apply to operation with fX = 5.0 MHz. Figure 6-19. Square-Wave Output Operation Timing
Count clock
TM0 count value
0000 0001 0002 Count start
N_1
N
0000 0001 0002
N_1
N
0000
CR00
N
N
TO0Note
Note
Initial value of TO0 output can be set by bits 2 and 3 (LVR0 and LVS0) of the 16-bit timer output control register (TOC0).
142
User's Manual U11302EJ4V0UM
CHAPTER 6
16-BIT TIMER/EVENT COUNTER
6.6 16-Bit Timer/Event Counter Operating Precautions
(1) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because the 16-bit timer register (TM0) is started asynchronously to the count pulse. Figure 6-20. 16-Bit Timer Register Start Timing
Count pulse
TM0 count value
0000H
0001H
0002H
0003H
0004H
Timer start
(2) 16-bit compare register setting Set the 16-bit compare register (CR00) to a value other than 0000H. Thus, when using the 16-bit compare register as an event counter, a one-pulse count operation cannot be carried out. (3) Operation after compare register change during timer count operation If the value after the 16-bit compare register (CR00) is changed is smaller than that of the 16-bit timer register (TM0), TM0 continues counting, overflows and then restarts counting from 0. Thus, if the value after CR00 change (M) is smaller than that before change (N), it is necessary to restart the timer after changing CR00. Figure 6-21. Timing After Compare Register Change During Timer Count Operation
Count pulse
CR00 captured value
N X_1
M
TM0 count value
X
FFFFH
0000H
0001H
0002H
Remark N > X > M
User's Manual U11302EJ4V0UM
143
CHAPTER 6
16-BIT TIMER/EVENT COUNTER
(4) Capture register data retention timing If the valid edge of the TI0/P00 pin is input during 16-bit capture register (CR01) read, CR01 holds the data without carrying out the capture operation. However, the interrupt request signal (INTTM0) is generated upon detection of the valid edge. Figure 6-22. Capture Register Data Retention Timing
Count pulse TM0 count value Edge input
N
N+1
N+2
M
M+1
M+2
INTTM0 Capture read signal CR01 captured value X N+1
Capture operation ignored
(5) Valid edge setting When using the INTP0/TI0/P00 pin as a timer input pin (TI0), stop the operation of the 16-bit timer by clearing bits 1 to 3 (TMC01 to TMC03) of the 16-bit timer mode control register (TMC0) to 0, 0, 0, before setting the valid edge of TI0. When using the INTP0/TI0/P00 pin as an external interrupt input pin (INTP0), the valid edge of INTP0 may be set while the 16-bit timer is operating.
144
User's Manual U11302EJ4V0UM
CHAPTER 7
8-BIT TIMER/EVENT COUNTER
7.1 8-Bit Timer/Event Counter Functions
The following two modes are available for the 8-bit timer/event counter incorporated in the PD780208 Subseries. * 8-bit timer/event counter mode: Two-channel 8-bit timer/event counter with each channel used separately
* 16-bit timer/event counter mode: Two-channel 8-bit timer/event counter used as 16-bit timer/event counter 7.1.1 8-bit timer/event counter mode 8-bit timer/event counters 1 and 2 (TM1 and TM2) have the following functions. * Interval timer * External event counter * Square-wave output
User's Manual U11302EJ4V0UM
145
CHAPTER 7
8-BIT TIMER/EVENT COUNTER
(1) 8-bit interval timer Interrupt requests are generated at the preset time intervals. Table 7-1. 8-Bit Timer/Event Counter Interval Time
Minimum Interval Time 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
Maximum Interval Time 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 211 x 1/fX (409.6 s) 212 x 1/fX (819.2 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 220 x 1/fX (209.7 ms)
Resolution 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 5.0 MHz.
146
User's Manual U11302EJ4V0UM
CHAPTER 7
8-BIT TIMER/EVENT COUNTER
(2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 7-2. 8-Bit Timer/Event Counter Square-Wave Output Ranges
Minimum Pulse Width 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
Maximum Pulse Width 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 211 x 1/fX (409.6 s) 212 x 1/fX (819.2 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 220 x 1/fX (209.7 ms)
Resolution 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 5.0 MHz.
User's Manual U11302EJ4V0UM
147
CHAPTER 7
8-BIT TIMER/EVENT COUNTER
7.1.2 16-bit timer/event counter mode (1) 16-bit interval timer Interrupt requests can be generated at the preset time intervals. Table 7-3. Interval Time When 8-Bit Timer/Event Counter Is Used as 16-Bit Timer/Event Counter
Minimum Interval Time 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
Maximum Interval Time 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 219 x 1/fX (104.9 ms) 220 x 1/fX (209.7 ms) 221 x 1/fX (419.4 ms) 222 x 1/fX (838.9 ms) 223 x 1/fX (1.7 s) 224 x 1/fX (3.4 s) 225 x 1/fX (6.7 s) 226 x 1/fX (13.4 s) 228 x 1/fX (53.7 s)
Resolution 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 5.0 MHz.
148
User's Manual U11302EJ4V0UM
CHAPTER 7
8-BIT TIMER/EVENT COUNTER
(2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 7-4. Square-Wave Output Ranges When 8-Bit Timer/Event Counter Is Used as 16-Bit Timer/Event Counter
Minimum Pulse Width 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
Maximum Pulse Width 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 219 x 1/fX (104.9 ms) 220 x 1/fX (209.7 ms) 221 x 1/fX (419.4 ms) 222 x 1/fX (838.9 ms) 223 x 1/fX (1.7 s) 224 x 1/fX (3.4 s) 225 x 1/fX (6.7 s) 226 x 1/fX (13.4 s) 228 x 1/fX (53.7 s)
Resolution 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 5.0 MHz.
User's Manual U11302EJ4V0UM
149
CHAPTER 7
8-BIT TIMER/EVENT COUNTER
7.2
8-Bit Timer/Event Counter Configuration
The 8-bit timer/event counter consists of the following hardware. Table 7-5. 8-Bit Timer/Event Counter Configuration
Item Timer register Registers Timer outputs Control registers Configuration 8 bits x 2 (TM1, TM2) 8-bit compare register: 2 (CR10, CR20) 2 (TO1, TO2) Timer clock select register 1 (TCL1) 8-bit timer mode control register (TMC1) 8-bit timer output control register (TOC1) Port mode register 3 (PM3)Note
Note
Refer to Figure 4-7 Block Diagram of P30 to P37.
150
User's Manual U11302EJ4V0UM
Figure 7-1. Block Diagram of 8-Bit Timer/Event Counter
Internal bus INTTM1 8-bit compare register (CR10) 8-bit compare register (CR20) Note
Selector
Match Match
Selector
8-bit timer/ event counter output controller 2 4
TO2/P32
CHAPTER 7
fx/22 to fx/210 fx/212
User's Manual U11302EJ4V0UM
Selector
8-bit timer register 1 (TM1) Clear 4 Selector
TI1/P33
8-bit timer register 2 (TM2) Clear
INTTM2
8-BIT TIMER/EVENT COUNTER
fx/212 TI2/P34
Selector
fx/2 to fx/2
2
10
4
8-bit timer/ event counter output controller 1 4
Note TO1/P31
TCL TCL TCL TCL TCL TCL TCL TCL 17 16 15 14 13 12 11 10
TMC12
TCE2
TCE1
LVS2 LVR2
TOC TOC TOE2 LVS1 LVR1 TOE1 15 11
Timer clock select register 1
8-bit timer mode control register Internal bus
8-bit timer output control register
151
Note
Refer to Figures 7-2 and 7-3 for details of 8-bit timer/event counter output controllers 1 and 2, respectively.
CHAPTER 7
8-BIT TIMER/EVENT COUNTER
Figure 7-2. Block Diagram of 8-Bit Timer/Event Counter Output Controller 1
Level F/F (LV1) LVR1 LVS1 TOC11 R Q S INV P31 output latch PM31Note TO1/P31
INTTM1
TOE1
Note
Bit 1 of port mode register 3 (PM3) The circuitry enclosed by the dotted line is the output controller. Figure 7-3. Block Diagram of 8-Bit Timer/Event Counter Output Controller 2
Remark
Level F/F (LV2) fSCK LVR2 LVS2 TOC15 R Q S INV P32 output latch PM32Note TO2/P32
INTTM2
TOE2
Note
Bit 2 of port mode register 3 (PM3)
Remarks 1. The circuitry enclosed by the dotted line is the output controller. 2. fSCK: Serial clock frequency
152
User's Manual U11302EJ4V0UM
CHAPTER 7
8-BIT TIMER/EVENT COUNTER
(1) 8-bit compare registers (CR10, CR20) These are 8-bit registers used to compare the value set to CR10 with the 8-bit timer register 1 (TM1) count value, and the value set to CR20 with the 8-bit timer register 2 (TM2) count value, and, if they match, generate an interrupt request (INTTM1 and INTTM2, respectively). CR10 and CR20 are set with an 8-bit memory manipulation instruction. They cannot be set with a 16-bit memory manipulation instruction. When the compare register is used as an 8-bit timer/event counter, values from 00H to FFH can be set. When the compare register is used as a 16-bit timer/event counter, values from 0000H to FFFFH can be set. RESET input makes CR10 and CR20 undefined. Cautions 1. When using the compare register as a 16-bit timer/event counter, be sure to set data after stopping timer operation. 2. When the values of CR10 and CR20 after changing are smaller than those of the 8-bit timer registers (TM1, TM2), TM1 and TM2 continue to count. When they overflow, counting starts again from 0. Therefore, it is necessary to restart the timer after changing the values of CR10 and CR20 if the values of CR10 and CR20 are smaller than the values before changing. (2) 8-bit timer registers 1, 2 (TM1, TM2) These are 8-bit registers used to count count pulses. When TM1 and TM2 are used in the separate mode, they should be read with an 8-bit memory manipulation instruction. When TM1 and TM2 are used in 16-bit timer mode, the 16-bit timer register (TMS) should be read with a 16-bit memory manipulation instruction. RESET input sets TM1 and TM2 to 00H.
7.3 8-Bit Timer/Event Counter Control Registers
The following four registers are used to control the 8-bit timer/event counter. * Timer clock select register 1 (TCL1) * 8-bit timer mode control register (TMC1) * 8-bit timer output control register (TOC1) * Port mode register 3 (PM3) (1) Timer clock select register 1 (TCL1) This register sets the count clock of 8-bit timer registers 1 and 2. TCL1 is set with an 8-bit memory manipulation instruction. RESET input sets TCL1 to 00H.
User's Manual U11302EJ4V0UM
153
CHAPTER 7
8-BIT TIMER/EVENT COUNTER
Figure 7-4. Format of Timer Clock Select Register 1
Symbol 7 6 5 4 3 2 1 0 Address FF41H After reset 00H R/W R/W
TCL1 TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL11 TCL10
8-bit timer register 1 count TCL13 TCL12 TCL11 TCL10 clock selection 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 TI1 falling edge TI1 rising edge fX/2 (2.5 MHz) fX/2 (1.25 MHz) fX/2 (625 kHz) fX/2 (313 kHz)
5 fX/2 (156 kHz) 4 3 2
fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.8 kHz) fX/210 (4.9 kHz) fX/212 (1.2 kHz) Setting prohibited
Other than above
8-bit timer register 2 count TCL17 TCL16 TCL15 TCL14 clock selection 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 TI2 falling edge TI2 rising edge fX/2 (2.5 MHz) fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.8 kHz) fX/210 (4.9 kHz) fX/212 (1.2 kHz) Setting prohibited
Other than above
Caution If TCL1 is to be rewritten with data other than identical data, the timer operation must be stopped first. Remarks 1. fX: Main system clock oscillation frequency
2. TI1: 8-bit timer register 1 input pin 3. TI2: 8-bit timer register 2 input pin 4. Figures in parentheses apply to operation with fX = 5.0 MHz.
154
User's Manual U11302EJ4V0UM
CHAPTER 7
8-BIT TIMER/EVENT COUNTER
(2) 8-bit timer mode control register (TMC1) This register enables/stops operation of 8-bit timer registers 1 and 2 and sets the operating mode of 8bit timer registers 1 and 2. TMC1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC1 to 00H. Figure 7-5. Format of 8-Bit Timer Mode Control Register
Symbol TMC1 7 0 6 0 5 0 4 0 3 0 2 <1> <0> Address FF49H After reset 00H R/W R/W
TMC12 TCE2 TCE1
TCE1 0 1
8-bit timer register 1 operation control Operation stopped (TM1 cleared to 0) Operation enabled
TCE2 0 1
8-bit timer register 2 operation control Operation stopped (TM2 cleared to 0) Operation enabled
TMC12 0 1
Operating mode selection 8-bit timer register x 2-channel mode (TM1, TM2) 16-bit timer register x 1-channel mode (TMS)
Cautions 1. Switch the operating mode after stopping timer operation. 2. When used as 16-bit timer register (TMS), TCE1 should be used for operation enable/stop.
User's Manual U11302EJ4V0UM
155
CHAPTER 7
8-BIT TIMER/EVENT COUNTER
(3) 8-bit timer output control register (TOC1) This register controls operation of 8-bit timer/event counter output controllers 1 and 2. It sets/resets the R-S flip-flops (LV1 and LV2) and enables/disables inversion and 8-bit timer output of 8bit timer registers 1 and 2. TOC1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TOC1 to 00H. Figure 7-6. Format of 8-Bit Timer Output Control Register
Symbol TOC1 <7> <6> 5 <4> <3> <2> 1 <0> Address FF4FH After reset 00H R/W R/W
LVS2 LVR2 TOC15 TOE2 LVS1 LVR1 TOC11 TOE1
TOE1 0 1
8-bit timer/event counter 1 output control Output disabled (port mode) Output enabled
TOC11 8-bit timer/event counter 1 timer output F/F control 0 1 Inverted operation disabled Inverted operation enabled
8-bit timer/event counter 1 timer output F/F status setting
LVS1 LVR1 0 0 1 1 0 1 0 1
Unchanged Timer output F/F reset (0) Timer output F/F set (1) Setting prohibited
TOE2 0 1
8-bit timer/event counter 2 output control Output disabled (port mode) Output enabled
TOC15 8-bit timer/event counter 2 timer output F/F control 0 1 Inverted operation disabled Inverted operation enabled
8-bit timer/event counter 2 timer output F/F status setting
LVS2 LVR2 0 0 1 1 0 1 0 1
Unchanged Timer output F/F reset (0) Timer output F/F set (1) Setting prohibited
Cautions 1. Be sure to set TOC1 after stopping timer operation. 2. After data setting, 0 is read from LVS1, LVS2, LVR1, and LVR2.
156
User's Manual U11302EJ4V0UM
CHAPTER 7
8-BIT TIMER/EVENT COUNTER
(4) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P31/TO1 and P32/TO2 pins for timer output, set PM31, PM32, and the output latches of P31 and P32 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH. Figure 7-7. Format of Port Mode Register 3
Symbol PM3
7
6
5
4
3
2
1
0
Address FF23H
After reset FFH
R/W R/W
PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
PM3n 0 1
P3n pin I/O mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off)
User's Manual U11302EJ4V0UM
157
CHAPTER 7
8-BIT TIMER/EVENT COUNTER
7.4 8-Bit Timer/Event Counter Operations
7.4.1 8-bit timer/event counter mode (1) Interval timer operations The 8-bit timer/event counter operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to the 8-bit compare registers (CR10 and CR20). When the count values of 8-bit timer registers 1 and 2 (TM1 and TM2) match the values set to CR10 and CR20, counting continues with the TM1 and TM2 values cleared to 0 and interrupt request signals (INTTM1 and INTTM2) are generated. The count clock of TM1 can be selected using bits 0 to 3 (TCL10 to TCL13) of timer clock select register 1 (TCL1). The count clock of TM2 can be selected using bits 4 to 7 (TCL14 to TCL17) of timer clock select register 1 (TCL1). For the operation when the value of the compare register is changed during timer count operation, refer to 7.5 8-Bit Timer/Event Counter Operating Precautions (3). Figure 7-8. Interval Timer Operation Timing
t
Count clock
TM1 count value
00
01
N
00 Clear N
01
N
00 Clear N
01
N
Count start CR10 N
N
INTTM1
Interrupt request acknowledgment Interrupt request acknowledgment TO1
Interval time
Interval time
Interval time
Remark
Interval time = (N + 1) x t: N = 00H to FFH
158
User's Manual U11302EJ4V0UM
CHAPTER 7
8-BIT TIMER/EVENT COUNTER
Table 7-6. 8-Bit Timer/Event Counter 1 Interval Time
TCL13 0 0 0 0 0 1 1 1 1 1 1 1 1 TCL12 0 0 1 1 1 0 0 0 0 1 1 1 1 TCL11 0 0 0 1 1 0 0 1 1 0 0 1 1 TCL10 0 1 1 0 1 0 1 0 1 0 1 0 1 Minimum Interval Time TI1 input cycle TI1 input cycle 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) Setting prohibited Maximum Interval Time 28 x TI1 input cycle 28 x TI1 input cycle 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 211 x 1/fX (409.6 s) 212 x 1/fX (819.2 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 220 x 1/fX (209.7 ms) Resolution TI1 input edge cycle TI1 input edge cycle 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
Other than above
Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 5.0 MHz. Table 7-7. 8-Bit Timer/Event Counter 2 Interval Time
TCL17 0 0 0 0 0 1 1 1 1 1 1 1 1 TCL16 0 0 1 1 1 0 0 0 0 1 1 1 1 TCL15 0 0 0 1 1 0 0 1 1 0 0 1 1 TCL14 0 1 1 0 1 0 1 0 1 0 1 0 1 Minimum Interval Time TI2 input cycle TI2 input cycle 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) Setting prohibited Maximum Interval Time 28 x TI2 input cycle 28 x TI2 input cycle 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 211 x 1/fX (409.6 s) 212 x 1/fX (819.2 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 220 x 1/fX (209.7 ms) Resolution TI2 input edge cycle TI2 input edge cycle 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
Other than above
Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 5.0 MHz.
User's Manual U11302EJ4V0UM
159
CHAPTER 7
8-BIT TIMER/EVENT COUNTER
(2) External event counter operation The external event counter counts the number of external clock pulses input to the TI1/P33 and TI2/P34 pins using 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 and TM2 are incremented each time the valid edge specified by timer clock select register 1 (TCL1) is input. Either the rising or falling edge can be selected. When the TM1 and TM2 count values match the values of the 8-bit compare registers (CR10 and CR20), TM1 and TM2 are cleared to 0 and interrupt request signals (INTTM1 and INTTM2) are generated. Figure 7-9. External Event Counter Operation Timing (with Rising Edge Specified)
TI1 pin input
TM1 count value
00
01
02
03
04
05
N-1
N
00
01
02
03
CR10
N
INTTM1
Remark N = 00H to FFH
160
User's Manual U11302EJ4V0UM
CHAPTER 7
8-BIT TIMER/EVENT COUNTER
(3) Square-wave output operation The 8-bit timer/event counter outputs a square wave of any frequency with the value preset to the 8-bit compare register (CR10, CR20) as the interval. The TO1/P31 or TO2/P32 pin output status is reversed at intervals of the count value preset to CR10 or CR20 by setting bit 0 (TOE1) or bit 4 (TOE2) of the 8-bit timer output control register (TOC1) to 1. This enables a square wave with any selected frequency to be output. Table 7-8. 8-Bit Timer/Event Counter Square-Wave Output Ranges
TCL13 0 0 0 1 1 1 1 1 1 1 1 TCL12 1 1 1 0 0 0 0 1 1 1 1 TCL11 0 1 1 0 0 1 1 0 0 1 1 TCL10 1 0 1 0 1 0 1 0 1 0 1 Minimum Pulse Width 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) Maximum Pulse Width 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 211 x 1/fX (409.6 s) 212 x 1/fX (819.2 s) 213 x 1/fX (1.64 ms) 214 x 1/fX (3.28 ms) 215 x 1/fX (6.55 ms) 216 x 1/fX (13.1 ms) 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 220 x 1/fX (209.7 ms) Resolution 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
Remarks 1. fX: Main system clock oscillation frequency 2. TCL10 to TCL13: Bits 0 to 3 of timer clock select register 1 (TCL1) 3. Figures in parentheses apply to operation with fX = 5.0 MHz. Figure 7-10. Square-Wave Output Operation Timing
Count clock
TM1 count value
00
01
02
N-1
N
00
01
02
N-1
N
00
Count start CR10 N N
TO1Note
Note
Initial value of TO1 output can be set using bits 2 and 3 (LVR1 and LVS1) of the 8-bit timer output control register (TOC1).
User's Manual U11302EJ4V0UM
161
CHAPTER 7
8-BIT TIMER/EVENT COUNTER
7.4.2 16-bit timer/event counter mode When bit 2 (TMC12) of the 8-bit timer mode control register (TMC1) is set to 1, the 16-bit timer/event counter mode is set. In this mode, the count clock is selected using bits 0 to 3 (TCL10 to TCL13) of the timer clock select register (TCL1). The overflow signal of 8-bit timer/event counter 1 (TM1) is used as the count clock of 8-bit timer/event counter 2 (TM2). Count operation enable/disable in this mode is selected using bit 0 (TCE1) of TMC1. (1) Interval timer operations The 8-bit timer/event counter operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to the 8-bit compare registers (CR10 and CR20). When setting a count value, set the value of the higher 8 bits to CR20 and the value of the lower 8 bits to CR10. For the count value (interval time) that can be set, refer to Table 7-9. When the 8-bit timer register 1 (TM1) and CR10 values match and the 8-bit timer register 2 (TM2) and CR20 values match, counting continues with the TM1 and TM2 values cleared to 0 and the interrupt request signal (INTTM2) is generated. For the operation timing of the interval timer, refer to Figure 7-11. The count clock can be selected using bits 0 to 3 (TCL10 to TCL13) of the timer clock select register (TCL1). The overflow signal of TM1 is used as the count clock of TM2. Figure 7-11. Interval Timer Operation Timing
t
Count clock
TMS (TM1, TM2) count value
0000 0001 Count start
N
0000 Clear N
0001
N
0000 Clear N
0001
N
CR10, CR20
N
N
INTTM2
Interrupt request acknowledgment Interrupt request acknowledgment TO2
Interval time
Interval time
Interval time
Remark Interval time = (N + 1) x t: N = 0000H to FFFFH
162
User's Manual U11302EJ4V0UM
CHAPTER 7
8-BIT TIMER/EVENT COUNTER
Caution Even if the 16-bit timer/event counter mode is used, when the TM1 count value matches the CR10 value, an interrupt request (INTTM1) is generated and the F/F of 8-bit timer/event counter output controller 1 is inverted. Thus, when using the 8-bit timer/event counter as a 16-bit interval timer, set the mask flag TMMK1 to 1 to disable INTTM1 acknowledgment. When reading the 16-bit timer register (TMS) count value, use a 16-bit memory manipulation instruction. Table 7-9. Interval Time When 2-Channel 8-Bit Timer/Event Counter (TM1 and TM2) Is Used as 16-Bit Timer/Event Counter
TCL13 0 0 0 0 0 1 1 1 1 1 1 1 1 TCL12 0 0 1 1 1 0 0 0 0 1 1 1 1 TCL11 0 0 0 1 1 0 0 1 1 0 0 1 1 TCL10 0 1 1 0 1 0 1 0 1 0 1 0 1 Minimum Interval Time TI1 input cycle TI1 input cycle 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) Setting prohibited Maximum Interval Time 28 x TI1 input cycle 28 x TI1 input cycle 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 219 x 1/fX (104.9 ms) 220 x 1/fX (209.7 ms) 221 x 1/fX (419.4 ms) 222 x 1/fX (838.9 ms) 223 x 1/fX (1.7 s) 224 x 1/fX (3.4 s) 225 x 1/fX (6.7 s) 226 x 1/fX (13.4 s) 228 x 1/fX (53.7 s) Resolution TI1 input edge cycle TI1 input edge cycle 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
Other than above
Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 5.0 MHz.
User's Manual U11302EJ4V0UM
163
CHAPTER 7
8-BIT TIMER/EVENT COUNTER
(2) External event counter operations The external event counter counts the number of external clock pulses input to the TI1/P33 pin by using the two channels of 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 is incremented each time the valid edge specified by timer clock select register 1 (TCL1) is input. If TM1 overflows as a result, the overflow signal is used as the count clock, and TM2 is incremented. Either the rising or falling edge can be selected. When the count value of TM1 and TM2 matches the value of the 8-bit compare registers (CR10 and CR20), both TM1 and TM2 are cleared to 0 and the interrupt request signal (INTTM2) is generated. Figure 7-12. External Event Counter Operation Timing (with Rising Edge Specified)
TI1 pin input
TMS (TM1, TM2) count value
0000 0001
0002 0003 0004 0005
N-1
N
0000 0001 0002 0003
CR10, CR20
N
INTTM2
Caution Even in the 16-bit timer/event counter mode, an interrupt request (INTTM1) will be generated when the TM1 count value matches the CR10 value, inverting the flip-flop of 8-bit timer/event counter output controller 1. Thus, when using the 8-bit timer/event counters as a 16-bit interval timer, set the mask flag TMMK1 to 1 to disable INTTM1 acknowledgment. When reading the 16-bit timer register (TMS) count value, use a 16-bit memory manipulation instruction.
164
User's Manual U11302EJ4V0UM
CHAPTER 7
8-BIT TIMER/EVENT COUNTER
(3) Square-wave output operation Square-wave signals can be generated at the user-specified frequency. The frequency or pulse interval is determined by the value preset in the 8-bit compare registers (CR10 and CR20). To set a count value, set the value of the higher 8 bits to CR20, and the value of the lower 8 bits to CR10. The TO2/P32 pin output status is reversed at intervals of the count value preset to CR10 and CR20 by setting bit 4 (TOE2) of the 8-bit timer output control register (TOC1) to 1. This enables a square wave with any selected frequency to be output. Table 7-10. Square-Wave Output Ranges When 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) Are Used as 16-Bit Timer/Event Counter
TCL13 0 0 0 1 1 1 1 1 1 1 1 TCL12 1 1 1 0 0 0 0 1 1 1 1 TCL11 0 1 1 0 0 1 1 0 0 1 1 TCL10 1 0 1 0 1 0 1 0 1 0 1 Minimum Pulse Width 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s) Maximum Pulse Width 217 x 1/fX (26.2 ms) 218 x 1/fX (52.4 ms) 219 x 1/fX (104.9 ms) 220 x 1/fX (209.7 ms) 221 x 1/fX (419.4 ms) 222 x 1/fX (838.9 ms) 223 x 1/fX (1.7 s) 224 x 1/fX (3.4 s) 225 x 1/fX (6.7 s) 226 x 1/fX (13.4 s) 228 x 1/fX (53.7 s) Resolution 2 x 1/fX (400 ns) 22 x 1/fX (800 ns) 23 x 1/fX (1.6 s) 24 x 1/fX (3.2 s) 25 x 1/fX (6.4 s) 26 x 1/fX (12.8 s) 27 x 1/fX (25.6 s) 28 x 1/fX (51.2 s) 29 x 1/fX (102.4 s) 210 x 1/fX (204.8 s) 212 x 1/fX (819.2 s)
Remarks 1. fX: Main system clock oscillation frequency 2. TCL10 to TCL13: Bits 0 to 3 of timer clock select register 1 (TCL1) 3. Figures in parentheses apply to operation with fX = 5.0 MHz. Figure 7-13. Square-Wave Output Operation Timing
Count clock TM1 TM2 CR10 CR20 TO2
00H 00H N M Interval time 01H N N+1 FFH 00H 01H FFH 00H 02H FFH 00H 01H M-1 M N 00H 01H 00H
Count start
Level reverse Counter clear
User's Manual U11302EJ4V0UM
165
CHAPTER 7
8-BIT TIMER/EVENT COUNTER
7.5 8-Bit Timer/Event Counter Operating Precautions
(1) Timer start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer registers 1 and 2 (TM1 and TM2) are started asynchronously to the count pulse. Figure 7-14. 8-Bit Timer Register Start Timing
Count pulse
TM1, TM2 count value
00H
01H
02H
03H
04H
Timer start
(2) 8-bit compare registers 1 and 2 settings The 8-bit compare registers (CR10 and CR20) can be set to 00H. Thus, when an 8-bit compare register is used as an event counter, a one-pulse count operation can be carried out. When the 8-bit compare registers are used as a 16-bit timer/event counter, write data to CR10 and CR20 after setting bit 0 (TCE1) of the 8-bit timer mode control register (TMC1) to 0 and stopping timer operation. Figure 7-15. External Event Counter Operation Timing
TI1, TI2 input
CR10, CR20
00H
TM1, TM2 count value
00H
00H
00H
00H
TO1, TO2
Interrupt request signal
166
User's Manual U11302EJ4V0UM
CHAPTER 7
8-BIT TIMER/EVENT COUNTER
(3) Operation after compare register change during timer count operation If the values after the 8-bit compare registers (CR10 and CR20) are changed are smaller than those of the 8-bit timer registers (TM1 and TM2), TM1 and TM2 continue counting, overflow and then restart counting from 0. Thus, if the value after CR10 and CR20 (M) change is smaller than that before the change (N), it is necessary to restart the timer after changing CR10 and CR20. Figure 7-16. Timing After Compare Register Change During Timer Count Operation
Count pulse
CR10, CR20
N X_1
M
TM1, TM2 count value
X
FFH
00H
01H
02H
Remark
N>X>M
User's Manual U11302EJ4V0UM
167
CHAPTER 8
WATCH TIMER
8.1 Watch Timer Functions
The watch timer has the following functions. * Watch timer * Interval timer The watch timer and the interval timer can be used simultaneously. (1) Watch timer When the 32.768 kHz subsystem clock is used, a flag (WTIF) is set at 0.5-second or 0.25-second intervals. In addition, when the 4.19 MHz (standard: 4.194304 MHz) main system clock is used, a flag (WTIF) is set at 0.5-second or 1-second intervals. Caution 0.5-second intervals cannot be generated with the 5.0 MHz main system clock. Switch to the 32.768 kHz subsystem clock to generate 0.5-second intervals. (2) Interval timer Interrupt requests (INTTM3) are generated at the preset time interval. Table 8-1. Interval Timer Interval Time
Interval Time 212 x 1/fX 2 2
13
When Operated at fX = 5.0 MHz 819 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms 26.2 ms
When Operated at fX = 4.19 MHz 978 s 1.96 ms 3.91 ms 7.82 ms 15.6 ms 31.3 ms
When Operated at fXT = 32.768 kHz 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms
x 1/fX x 1/fX
14
215 x 1/fX 216 x 1/fX 2
17
x 1/fX
fX: Main system clock oscillation frequency fXT: Subsystem clock oscillation frequency
168
User's Manual U11302EJ4V0UM
CHAPTER 8
WATCH TIMER
8.2 Watch Timer Configuration
The watch timer consists of the following hardware. Table 8-2. Watch Timer Configuration
Item Counter Control registers 5 bits x 1 Timer clock select register 2 (TCL2) Watch timer mode control register (TMC2) Configuration
8.3 Watch Timer Control Registers
The following two registers are used to control the watch timer. * Timer clock select register 2 (TCL2) * Watch timer mode control register (TMC2) (1) Timer clock select register 2 (TCL2) (See Figure 8-2) This register sets the watch timer count clock. TCL2 is set with an 8-bit memory manipulation instruction. RESET input sets TCL2 to 00H. Remark Besides setting the watch timer count clock, TCL2 sets the watchdog timer count clock and buzzer output frequency.
User's Manual U11302EJ4V0UM
169
Selector
fW
Prescaler
Selector
fX/2
8
Clear
Selector
Selector
170
TMC21 fXT fW 4 2 fW 5 2
User's Manual U11302EJ4V0UM
Figure 8-1. Watch Timer Block Diagram
5-bit counter Clear
fW 214
INTWT
fW 6 2
fW 7 2
fW 8 2
fW 9 2
fW 213
INTTM3
CHAPTER 8
3
WATCH TIMER
TCL24
TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20
Timer clock select register 2 Internal bus
Watch timer mode control register
CHAPTER 8
WATCH TIMER
Figure 8-2. Format of Timer Clock Select Register 2
Symbol 7 6 5 4 3 0 2 1 0 Address FF42H After reset 00H R/W R/W
TCL2 TCL27 TCL26 TCL25 TCL24
TCL22 TCL21 TCL20
Count clock selection TCL22 TCL21 TCL20 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Watchdog timer mode
Interval timer mode fX/2 (313 kHz)
5 fX/2 (156 kHz) 4
fX/2 (625 kHz) fX/2 (313 kHz) fX/25 (156 kHz) fX/2 (78.1 kHz) fX/27 (39.1 kHz)
8 fX/2 (19.5 kHz) 9 6 4
3
fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz)
9 fX/2 (9.8 kHz) 10
fX/2 (9.8 kHz)
11 fX/2 (2.4 kHz)
fX/2 (4.9 kHz)
12 fX/2 (1.2 kHz)
Note TCL24 Watch timer count clock selection
0 1
fX/28 (19.5 kHz) fXT (32.768 kHz)
TCL27 TCL26 TCL25 Buzzer output frequency selection 0 1 1 1 1 x 0 0 1 1 x 0 1 0 1 Buzzer output disabled fX/210 (4.9 kHz) fX/2 (2.4 kHz)
12 fX/2 (1.2 kHz) 11
Setting prohibited
Note
When using a main system clock of 1.25 MHz or less and the VFD controller/driver, select fX/28 as the count clock for the watch timer.
Caution
When changing the count clock, be sure to stop operation of the watch timer before rewriting TCL2 (stopping operation is not necessary when rewriting the same data).
Remarks 1. fX: Main system clock oscillation frequency 2. fXT: Subsystem clock oscillation frequency 3. x: don't care 4. Figures in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz.
User's Manual U11302EJ4V0UM
171
CHAPTER 8
WATCH TIMER
(2) Watch timer mode control register (TMC2) This register sets the watch timer operating mode, watch flag set time and prescaler interval time and enables/disables prescaler and 5-bit counter operations. TMC2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC2 to 00H. Figure 8-3. Format of Watch Timer Mode Control Register
Symbol TMC2 7 0 6 5 4 3 2 1 0 Address FF4AH After reset 00H R/W R/W
TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20
TMC23 TMC20 Watch flag set time selection 0 0 1 0 1 1 213/fW (0.25 s) 25/fW (977 s) 24/fW (488 s) 214/fW (0.5 s)
TMC21 Prescaler operation controlNote 0 1 Clear after operation stops Operation enable
TMC22 5-bit counter operation control 0 1 Clear after operation stops Operation enable
TMC26 TMC25 TMC24 Prescaler interval time selection 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 24/fW (488 s) 25/fW (977 s) 26/fW (1.95 ms) 27/fW (3.91 ms) 28/fW (7.81 ms) 29/fW (15.6 ms) Setting prohibited
Other than above
Note
Do not frequently clear the prescaler when using the watch timer.
Remarks 1. fW: Watch timer clock frequency (fX/28 or fXT) 2. Figures in parentheses apply to operation with fW = 32.768 kHz.
172
User's Manual U11302EJ4V0UM
CHAPTER 8
WATCH TIMER
8.4 Watch Timer Operations
8.4.1 Watch timer operation When the 32.768 kHz subsystem clock is used, the timer operates as a watch timer with a 0.5-second or 0.25second interval. In addition, when the 4.19 MHz main system clock is used, the timer can operate as a watch timer with a 0.5-second or 1-second interval. The watch timer sets the test input flag (WTIF) to 1 at a constant time interval. The standby state (STOP mode/ HALT mode) can be cleared by setting WTIF to 1. When bit 2 (TMC22) of the watch timer mode control register (TMC2) is set to 0, the 5-bit counter is cleared and the count operation stops. For simultaneous operation of the interval timer, zero-second start can be achieved by setting TMC22 to 1 again after setting TMC22 to 0 (maximum error: 26.2 ms when operated at 5.0 MHz). 8.4.2 Interval timer operation The watch timer operates as an interval timer that generates interrupt requests repeatedly at an interval of the preset count value. The interval time can be selected using bits 4 to 6 (TMC24 to TMC26) of the watch timer mode control register (TMC2). Table 8-3. Interval Timer Interval Time
When Operated at fX = 5.0 MHz 819 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms 26.2 ms When Operated at fX = 4.19 MHz 978 s 1.96 ms 3.91 ms 7.82 ms 15.6 ms 31.3 ms When Operated at fXT = 32.768 kHz 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms
TMC26 0 0 0 0 1 1
TMC25 0 0 1 1 0 0
TMC24 0 1 0 1 0 1
Interval Time 24 x 1/fW 2 x 1/fW 26 x 1/fW 27 x 1/fW 28 x 1/fW 2 x 1/fW Setting prohibited
9 5
Other than above
fX: Main system clock oscillation frequency fXT: Subsystem clock oscillation frequency fW: Watch timer clock frequency (fX/28 or fXT)
User's Manual U11302EJ4V0UM
173
CHAPTER 9
WATCHDOG TIMER
9.1 Watchdog Timer Functions
The watchdog timer has the following functions. * Watchdog timer * Interval timer Caution Select the watchdog timer mode or the interval timer mode using the watchdog timer mode register (WDTM) (the watchdog timer and interval timer cannot be used at the same time). (1) Watchdog timer mode This mode detects an inadvertent program loop. Upon detection of the program loop, a non-maskable interrupt request or RESET can be generated. Table 9-1. Watchdog Timer Program Loop Detection Time
Program Loop Detection Time 211 x 1/fX 2 2
12
When Operated at fX = 5.0 MHz 410 s 819 s 1.64 ms 3.28 ms
Program Loop Detection Time 215 x 1/fX 2 2
16
When Operated at fX = 5.0 MHz 6.55 ms 13.1 ms 26.2 ms 104.9 ms
x 1/fX x 1/fX
x 1/fX x 1/fX
13
17
214 x 1/fX
219 x 1/fX
fX: Main system clock oscillation frequency
(2) Interval timer mode Interrupt requests are generated at the preset time intervals. Table 9-2. Interval Time
Interval Time 212 x 1/fX 213 x 1/fX 214 x 1/fX 2
15
When Operated at fX = 5.0 MHz 819 s 1.64 ms 3.28 ms 6.55 ms
Interval Time 216 x 1/fX 217 x 1/fX 218 x 1/fX 2
20
When Operated at fX = 5.0 MHz 13.1 ms 26.2 ms 52.4 ms 210 ms
x 1/fX
x 1/fX
fX: Main system clock oscillation frequency
174
User's Manual U11302EJ4V0UM
CHAPTER 9
WATCHDOG TIMER
9.2 Watchdog Timer Configuration
The watchdog timer consists of the following hardware. Table 9-3. Watchdog Timer Configuration
Item Control registers Configuration Timer clock select register 2 (TCL2) Watchdog timer mode register (WDTM)
User's Manual U11302EJ4V0UM
175
Selector
Selector
176
fX 4 2 8-bit prescaler fWDT fWDT fWDT fWDT fWDT fWDT fWDT fWDT 2 3 4 5 6 8 2 2 2 2 2 2 2 fX 3 2
User's Manual U11302EJ4V0UM
Figure 9-1.
Watchdog Timer Block Diagram
Internal bus
TMMK4 RUN Clear 8-bit counter Controller TMIF4 INTWDT maskable interrupt request RESET INTWDT non-maskable interrupt request 3
CHAPTER 9 WATCHDOG TIMER
TCL22 TCL21 TCL20 Timer clock select register 2 Internal bus
RUN
WDTM4 WDTM3 Watchdog timer mode register
CHAPTER 9
WATCHDOG TIMER
9.3 Watchdog Timer Control Registers
The following two registers are used to control the watchdog timer. * Timer clock select register 2 (TCL2) * Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer count clock. TCL2 is set with an 8-bit memory manipulation instruction. RESET input sets TCL2 to 00H. Remark Besides setting the watchdog timer count clock, TCL2 sets the watch timer count clock and buzzer output clock.
User's Manual U11302EJ4V0UM
177
CHAPTER 9
WATCHDOG TIMER
Figure 9-2. Format of Timer Clock Select Register 2
Symbol 7 6 5 4 3 0 2 1 0 Address FF42H After reset 00H R/W R/W
TCL2 TCL27 TCL26 TCL25 TCL24
TCL22 TCL21 TCL20
Count clock selection TCL22 TCL21 TCL20 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Watchdog timer mode fX/23 (625 kHz) fX/2 (313 kHz) fX/2 (156 kHz) fX/2 (78.1 kHz) fX/27 (39.1 kHz) fX/2 (19.5 kHz) fX/2 (9.8 kHz)
11 fX/2 (2.4 kHz) 9 8 6 5 4
Interval timer mode fX/2 (313 kHz) fX/2 (156 kHz) fX/2 (78.1 kHz) fX/2 (39.1 kHz) fX/28 (19.5 kHz)
9 fX/2 (9.8 kHz) 10 7 6 5 4
fX/2 (4.9 kHz)
12 fX/2 (1.2 kHz)
Note TCL24 Watch timer count clock selection
0 1
fX/28 (19.5 kHz) fXT (32.768 kHz)
TCL27 TCL26 TCL25 Buzzer output frequency selection 0 1 1 1 1 x 0 0 1 1 x 0 1 0 1 Buzzer output disabled fX/210 (4.9 kHz) fX/2 (2.4 kHz) fX/2 (1.2 kHz) Setting prohibited
12 11
Note
fX/28 must be selected as the watch timer count clock when using a main system clock of 1.25 MHz or less and the VFD controller/driver.
Caution
Changing the count clock (rewriting TCL20 to TCL22) after watchdog timer operation has started is prohibited.
Remarks 1. fX: Main system clock oscillation frequency 2. fXT: Subsystem clock oscillation frequency 3. x: don't care 4. Figures in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz.
178
User's Manual U11302EJ4V0UM
CHAPTER 9
WATCHDOG TIMER
(2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 9-3. Format of Watchdog Timer Mode Register
Symbol WDTM <7> RUN 6 0 5 0 4 3 2 0 1 0 0 0 Address FFF9H After reset 00H R/W R/W
WDTM4 WDTM3
WDTM4 WDTM3 Watchdog timer operating mode selection 0 x
Note 1
Interval timer modeNote 2 (Maskable interrupt request occurs upon generation of an overflow.) Watchdog timer mode 1 (Non-maskable interrupt request occurs upon generation of an overflow.) Watchdog timer mode 2 (Reset operation is activated upon generation of an overflow.)
1
0
1
1
RUN 0 1
Watchdog timer operation selectionNote 3 Count stop Counter is cleared and counting starts.
Notes 1. Once set to 1, WDTM3 and WDTM4 cannot be cleared to 0 by software. 2. Starts operation as an interval timer as soon as RUN is set to 1. 3. Once set to 1, RUN cannot be cleared to 0 by software. Thus, once counting starts, it can only be stopped by RESET input. Cautions 1. When RUN is set to 1 so that the watchdog timer is cleared, the actual overflow time is up to 0.5% shorter than the time set by timer clock select register 2 (TCL2). 2. When using watchdog timer mode 1 and 2, make sure that the interrupt request flag (TMIF4) is set to 0 before setting WDTM4 to 1. If WDTM4 is set to 1 while TMIF4 is 1, a non-maskable interrupt request occurs regardless of the contents of WDTM3. Remark x: don't care
User's Manual U11302EJ4V0UM
179
CHAPTER 9
WATCHDOG TIMER
9.4 Watchdog Timer Operations
9.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer operates to detect an inadvertent program loop. The watchdog timer count clock (program loop detection time interval) can be selected using bits 0 to 2 (TCL20 to TCL22) of timer clock select register 2 (TCL2). The watchdog timer starts by setting bit 7 (RUN) of WDTM to 1. After the watchdog timer is started, set RUN to 1 within the set program loop detection time interval. The watchdog timer can be cleared and counting is started by setting RUN to 1. If RUN is not set to 1 and the program loop detection time elapses, a system reset or a nonmaskable interrupt request is generated according to the value of WDTM bit 3 (WDTM3). The watchdog timer continues operating in the HALT mode but it stops in the STOP mode. Thus, set RUN to 1 before the STOP mode is set, clear the watchdog timer and then execute the STOP instruction. Cautions 1. The actual program loop detection time may be shorter than the set time by a maximum of 0.5%. 2. When the subsystem clock is selected for the CPU clock, the watchdog timer count operation is stopped. Table 9-4. Watchdog Timer Program Loop Detection Time
TCL22 0 0 0 0 1 1 1 1 TCL21 0 0 1 1 0 0 1 1 TCL20 0 1 0 1 0 1 0 1 Program Loop Detection Time 211 x 1/fX 2 2
12
fX = 5.0 MHz 410 s 819 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms 26.2 ms 105.0 ms
x 1/fX x 1/fX
13
214 x 1/fX 215 x 1/fX 2 2
16
x 1/fX x 1/fX
17
219 x 1/fX
fX: Main system clock oscillation frequency
180
User's Manual U11302EJ4V0UM
CHAPTER 9
WATCHDOG TIMER
9.4.2 Interval timer operation The watchdog timer operates as an interval timer that generates interrupt requests repeatedly at intervals of the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is cleared to 0. The count clock (interval time) can be selected by bits 0 to 2 (TCL20 to TCL22) of timer clock select register 2 (TCL2). By setting bit 7 (RUN) of WDTM to 1, the watchdog timer starts operation as an interval timer. When the watchdog timer operates as an interval timer, the interrupt mask flag (TMMK4) and priority specification flag (TMPR4) are validated and a maskable interrupt request (INTWDT) can be generated. Among the maskable interrupt requests, INTWDT has the highest default priority. The interval timer continues operating in the HALT mode but it stops in the STOP mode. Thus, set RUN to 1 before the STOP mode is set, clear the interval timer and then execute the STOP instruction. Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (with the watchdog timer mode selected), the interval timer mode is not set unless RESET input is applied. 2. The interval time just after setting by WDTM may be shorter than the set time by a maximum of 0.5%. 3. When the subsystem clock is selected for the CPU clock, the watchdog timer count operation is stopped. Table 9-5. Interval Timer Interval Time
TCL22 0 0 0 0 1 1 1 1 TCL21 0 0 1 1 0 0 1 1 TCL20 0 1 0 1 0 1 0 1 2
12
Interval Time x 1/fX
fX = 5.0 MHz 819 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms 26.2 ms 52.4 ms 210.0 ms
213 x 1/fX 214 x 1/fX 2 2
15
x 1/fX x 1/fX
16
217 x 1/fX 218 x 1/fX 2
20
x 1/fX
fX: Main system clock oscillation frequency
User's Manual U11302EJ4V0UM
181
CHAPTER 10 CLOCK OUTPUT CONTROLLER
10.1 Clock Output Controller Functions
The clock output controller is used for carrier output during remote controlled transmission and clock output for supply to a peripheral LSI. The clock selected by timer clock select register 0 (TCL0) is output from the PCL/ P35 pin. Follow the procedure below to output clock pulses. [1] Select the clock pulse output frequency (with clock pulse output disabled) using bits 0 to 3 (TCL00 to TCL03) of TCL0. [2] Set the P35 output latch to 0. [3] Set bit 5 (PM35) of port mode register 3 (PM3) to 0 (set to output mode). [4] Set bit 7 (CLOE) of TCL0 to 1. Caution Remark Clock output cannot be used when the P35 output latch is set to 1. When clock output enable/disable is switched, the clock output controller does not output pulses with small widths (see the mark
* in Figure 10-1).
Figure 10-1. Remote Controlled Output Application Example
CLOE
PCL/P35 pin output
*
*
182
User's Manual U11302EJ4V0UM
CHAPTER 10
CLOCK OUTPUT CONTROLLER
10.2 Clock Output Controller Configuration
The clock output controller consists of the following hardware. Table 10-1. Clock Output Controller Configuration
Item Control registers Configuration Timer clock select register 0 (TCL0) Port mode register 3 (PM3)
Figure 10-2. Clock Output Controller Block Diagram
3
fX/2 fX/2
fX/24
5
fX/26 fX/27 fX/2
8
Selector
Synchronizing circuit
PCL/P35
fXT 4
CLOE TCL03 TCL02 TCL01 TCL00 Timer clock select register 0
P35 output latch
PM35 Port mode register 3
Internal bus
10.3 Clock Output Function Control Registers
The following two registers are used to control the clock output function. * Timer clock select register 0 (TCL0) * Port mode register 3 (PM3) (1) Timer clock select register 0 (TCL0) This register sets the PCL output clock. TCL0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TCL0 to 00H. Remark Besides setting the PCL output clock, TCL0 sets the 16-bit timer register count clock.
User's Manual U11302EJ4V0UM
183
CHAPTER 10
CLOCK OUTPUT CONTROLLER
Figure 10-3. Format of Timer Clock Select Register 0
Symbol <7> TCL0 6 5 4 3 2 1 0 Address FF40H After reset 00H R/W R/W
CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00
TCL03 TCL02 TCL01 TCL00 PCL output clock selection 0 0 1 1 1 1 1 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 1 0 1 0 1 0 fXT (32.768 kHz) fX/2 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz)
7 fX/2 (39.1 kHz) 3
fX/28 (19.5 kHz) Setting prohibited
Other than above
16-bit timer register count clock TCL06 TCL05 TCL04 selection 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 TI0 (valid edge specifiable) fX (5.0 MHz) fX/2 (2.5 MHz) fX/22 (1.25 MHz) fX/2 (625 kHz) Setting prohibited
3
Other than above
CLOE 0 1
PCL output control Output disabled Output enabled
Cautions 1. The TI0/P00/INTP0 pin valid edge is set by the external interrupt mode register (INTM0), and the sampling clock frequency is selected by the sampling clock select register (SCS). 2. When enabling PCL output, set TCL00 to TCL03, then set CLOE to 1 with a 1-bit memory manipulation instruction. 3. To read the count value when TI0 has been specified as the TM0 count clock, the value should be read from TM0, not from the 16-bit capture register (CR01). 4. If TCL0 is to be rewritten with data other than identical data, the timer operation must be stopped first. Remarks 1. fX: 2. fXT: Main system clock oscillation frequency Subsystem clock oscillation frequency
3. TI0: 16-bit timer/event counter input pin 4. TM0: 16-bit timer register 5. Figures in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz.
184
User's Manual U11302EJ4V0UM
CHAPTER 10
CLOCK OUTPUT CONTROLLER
(2) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P35/PCL pin for clock output, set PM35 and the output latch of P35 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH. Figure 10-4. Format of Port Mode Register 3
Symbol PM3 7 6 5 4 3 2 1 0 Address FF23H After reset FFH R/W R/W
PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
PM3n 0 1
P3n pin I/O mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off)
User's Manual U11302EJ4V0UM
185
CHAPTER 11
BUZZER OUTPUT CONTROLLER
11.1 Buzzer Output Controller Functions
The buzzer output controller outputs a 1.2 kHz, 2.4 kHz, or 4.9 kHz frequency square-wave. The buzzer frequency selected by timer clock select register 2 (TCL2) is output from the BUZ/P36 pin. Follow the procedure below to output the buzzer frequency. [1] Select the buzzer output frequency using bits 5 to 7 (TCL25 to TCL27) of TCL2. [2] Set the P36 output latch to 0. [3] Set bit 6 (PM36) of port mode register 3 (PM3) to 0 (set to output mode). Caution Buzzer output cannot be used when the P36 output latch is set to 1.
11.2 Buzzer Output Controller Configuration
The buzzer output controller consists of the following hardware. Table 11-1. Buzzer Output Controller Configuration
Item Control registers Configuration Timer clock select register 2 (TCL2) Port mode register 3 (PM3)
Figure 11-1. Buzzer Output Controller Block Diagram
fX/211 fX/212
Selector
fX/210
BUZ/P36
3
TCL27TCL26TCL25 Timer clock select register 2
P36 output latch
PM36 Port mode register 3
Internal bus
186
User's Manual U11302EJ4V0UM
CHAPTER 11
BUZZER OUTPUT CONTROLLER
11.3 Buzzer Output Function Control Registers
The following two registers are used to control the buzzer output function. * Timer clock select register 2 (TCL2) * Port mode register 3 (PM3) (1) Timer clock select register 2 (TCL2) This register sets the buzzer output frequency. TCL2 is set with an 8-bit memory manipulation instruction. RESET input sets TCL2 to 00H. Remark Besides setting the buzzer output frequency, TCL2 sets the watch timer count clock and the watchdog timer count clock.
User's Manual U11302EJ4V0UM
187
CHAPTER 11
BUZZER OUTPUT CONTROLLER
Figure 11-2. Format of Timer Clock Select Register 2
Symbol 7 6 5 4 3 0 2 1 0 Address FF42H After reset 00H R/W R/W
TCL2 TCL27 TCL26 TCL25 TCL24
TCL22 TCL21 TCL20
Count clock selection TCL22 TCL21 TCL20 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Watchdog timer mode
3 fX/2 (625 kHz) 4 fX/2 (313 kHz)
Interval timer mode fX/24 (313 kHz)
5 fX/2 (156 kHz)
fX/2 (156 kHz) fX/2 (78.1 kHz) fX/2 (39.1 kHz) fX/2 (19.5 kHz) fX/2 (9.8 kHz) fX/2 (2.4 kHz)
11 9 8 7 6
5
fX/26 (78.1 kHz) fX/2 (39.1 kHz) fX/2 (19.5 kHz)
9 fX/2 (9.8 kHz) 10 12 8 7
fX/2 (4.9 kHz) fX/2 (1.2 kHz)
TCL24 Watch timer count clock selection 0 1 fX/28 (19.5 kHz) fXT (32.768 kHz)
TCL27 TCL26 TCL25 Buzzer output frequency selection 0 1 1 1 1 x 0 0 1 1 x 0 1 0 1 Buzzer output disabled fX/210 (4.9 kHz) fX/2 (2.4 kHz) fX/2 (1.2 kHz) Setting prohibited
12 11
Cautions 1. Be sure to stop operation of the watch timer or buzzer to be changed before rewriting TCL2 (stopping operation is not necessary when rewriting the same data). The operation is stopped by the following methods. * Buzzer output: Input 0 to bit 7 (TCL27) of TCL2 * Watch timer: Input 0 to bit 2 (TMC22) of the watch timer mode control register (TMC2) 2. Changing the count clock (rewriting TCL20 to TCL22) after watchdog timer operation has started is prohibited. Remarks 1. fX: Main system clock oscillation frequency 2. fXT: Subsystem clock oscillation frequency 3. x: don't care 4. Figures in parentheses apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz.
188
User's Manual U11302EJ4V0UM
CHAPTER 11
BUZZER OUTPUT CONTROLLER
(2) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P36/BUZ pin for buzzer output, set PM36 and the output latch of P36 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH. Figure 11-3. Format of Port Mode Register 3
Symbol PM3
7
6
5
4
3
2
1
0
Address FF23H
After reset FFH
R/W R/W
PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
PM3n 0 1
P3n pin I/O mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off)
User's Manual U11302EJ4V0UM
189
CHAPTER 12
A/D CONVERTER
12.1 A/D Converter Functions
The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an 8-bit resolution. The conversion method is based on successive approximation and the conversion result is held in the 8-bit A/D conversion result register (ADCR). A/D conversion can be started in the following two ways. (1) Hardware start Conversion is started by trigger input (INTP3). (2) Software start Conversion is started by setting the A/D converter mode register (ADM). Select one channel of analog input from ANI0 to ANI7 and carry out A/D conversion. In the case of a hardware start, when A/D conversion finishes, the A/D converter stops and an interrupt request (INTAD) is generated. In the case of a software start, the A/D conversion operation is repeated. Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated.
12.2 A/D Converter Configuration
The A/D converter consists of the following hardware. Table 12-1. A/D Converter Configuration
Item Analog input Control registers Configuration 8 channels (ANI0 to ANI7) A/D converter mode register (ADM) A/D converter input select register (ADIS) Registers Successive approximation register (SAR) A/D conversion result register (ADCR)
190
User's Manual U11302EJ4V0UM
CHAPTER 12
A/D CONVERTER
Figure 12-1.
A/D Converter Block Diagram
Internal bus A/D converter input select register ADIS3 ADIS2 ADIS1 ADIS0
4 ANI0/P10
Note 1 Note 2
Series resistor string AVDD Sample & hold circuit
Tap selector
ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17
Selector
Selector
Voltage comparator
AVREF
AVSS
Successive approximation register (SAR)
3 ADM1 to ADM3
AVSS
INTP3/P03
Falling edge detector
Controller
INTAD INTP3
Trigger enable
3 FR1 FR0 ADM3 ADM2 ADM1 A/D conversion result register (ADCR)
CS
TRG
A/D converter mode register Internal bus
Notes 1. Selector to select the number of channels to be used for analog input 2. Selector to select the channel for A/D conversion
User's Manual U11302EJ4V0UM
191
CHAPTER 12
A/D CONVERTER
(1) Successive approximation register (SAR) This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string and holds the result from the most significant bit (MSB). When up to the least significant bit (LSB) is held (end of A/D conversion), the SAR contents are transferred to the A/D conversion result register (ADCR). (2) A/D conversion result register (ADCR) This register holds the A/D conversion result. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register (SAR). ADCR is read with an 8-bit memory manipulation instruction. RESET input makes ADCR undefined. (3) Sample & hold circuit The sample & hold circuit samples each analog input signal sequentially applied from the input circuit and sends it to the voltage comparator. This circuit holds the sampled analog input voltage value during A/D conversion. (4) Voltage comparator The voltage comparator compares the analog input with the series resistor string output voltage. (5) Series resistor string The series resistor string is connected between AVREF and AVSS and generates a voltage to be compared with the analog input. (6) ANI0 to ANI7 pins These are 8-channel analog input pins used to input the analog signals to undergo A/D conversion to the A/D converter. Except for the analog input pins selected by the A/D converter input select register (ADIS), these pins can be used as I/O port pins. Cautions 1. Use ANI0 to ANI7 input voltages within the specified range. If a voltage higher than or equal to AVREF or lower than or equal to AVSS is applied (even if within the absolute maximum ratings), the converted value of the corresponding channel becomes undefined and may adversely affect the converted values of other channels. 2. The analog input pins ANI0 to ANI7 also function as I/O port (port 1) pins. Pins used as analog inputs should be set to the input mode. When A/D conversion is performed with any of pins ANI0 to ANI7 selected, be sure not to execute an instruction that inputs data to port 1 while conversion is in progress, as this may reduce the conversion resolution. Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/ D conversion, the expected A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion.
192
User's Manual U11302EJ4V0UM
CHAPTER 12
A/D CONVERTER
(7) AVREF pin This pin inputs the A/D converter reference voltage. It converts signals input to ANI0 to ANI7 into digital signals according to the voltage applied between AVREF and AVSS. Caution A series resistor string of approximately 10 k is connected between the AVREF pin and the AVSS pin. Therefore, if the output impedance of the reference voltage source is high, this will result in series connection to the series resistor string between the AVREF pin and the AVSS pin, and there will be a large reference voltage error. (8) AVSS pin Ground potential pin of the A/D converter. It must be at the same level as the VSS pin even if the A/D converter is not used. (9) AVDD pin Analog power supply pin of the A/D converter. It must be at the same level as the VDD pin even if the A/D converter is not used.
User's Manual U11302EJ4V0UM
193
CHAPTER 12
A/D CONVERTER
12.3 A/D Converter Control Registers
The following two registers are used to control the A/D converter. * A/D converter mode register (ADM) * A/D converter input select register (ADIS) (1) A/D converter mode register (ADM) This register sets the analog input channel for A/D conversion, conversion time, conversion start/stop, and external trigger. ADM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADM to 01H.
194
User's Manual U11302EJ4V0UM
CHAPTER 12
A/D CONVERTER
Figure 12-2. Format of A/D Converter Mode Register
Symbol ADM <7> CS <6> TRG 5 FR1 4 3 2 1 0 1 Address After reset FF80H 01H R/W R/W
FR0 ADM3 ADM2 ADM1
ADM3 ADM2 ADM1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Analog input channel selection ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7
A/D conversion time selection Note 1 FR1 0 0 1 1 FR0 When operated at fX = 5.0 MHz 0 1 0 1 160/fX (32.0 s) 80/fX (setting prohibited 200/fX (40.0 s) Setting prohibited
Note 2
When operated at fX = 4.19 MHz 160/fX (38.1 s)
)
80/fX (19.1 s) 200/fX (47.7 s)
TRG 0 1
External trigger selection No external trigger (software start mode) Conversion started by external trigger (hardware start mode)
CS 0 1
A/D conversion operation control Operation stop Operation start
Notes 1. Set so that the A/D conversion time is 19.1 s or more. 2. Setting prohibited because the A/D conversion time is less than 19.1 s. Cautions 1. Bit 0 must be set to 1. 2. In order to reduce the power consumption of the A/D converter when the standby function is working, clear bit 7 (CS) of this register to 0 to stop the A/D conversion operation before executing the HALT or STOP instruction. 3. When restarting a stopped A/D conversion operation, start the A/D conversion operation after clearing the interrupt request flag (ADIF) to 0. Remark fX: Main system clock oscillation frequency
User's Manual U11302EJ4V0UM
195
CHAPTER 12
A/D CONVERTER
(2) A/D converter input select register (ADIS) This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels or ports. The pins that are not selected for analog input pins can be used as I/O port pins. ADIS is set with an 8-bit memory manipulation instruction. RESET input sets ADIS to 00H. Cautions 1. Set the analog input channel using the following procedure. [1] Set the number of analog input channels using ADIS. [2] Using the A/D converter mode register (ADM), select the channel to undergo A/ D conversion among the channels which were set to analog input using ADIS. 2. No internal pull-up resistor can be connected to the channels set to analog input using ADIS, irrespective of the value of bit 1 (PUO1) of the pull-up resistor option register (PUO). Figure 12-3. Format of A/D Converter Input Select Register
Symbol ADIS 7 0 6 0 5 0 4 0 3 2 1 0 Address After reset FF84H 00H R/W R/W
ADIS3 ADIS2 ADIS1 ADIS0
ADIS3 ADIS2 ADIS1 ADIS0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0
Analog input channel count selection No analog input channels (P10 to P17) 1 channel (ANI0, P11 to P17) 2 channels (ANI0, ANI1, P12 to P17) 3 channels (ANI0 to ANI2, P13 to P17) 4 channels (ANI0 to ANI3, P14 to P17) 5 channels (ANI0 to ANI4, P15 to P17) 6 channels (ANI0 to ANI5, P16, P17) 7 channels (ANI0 to ANI6, P17) 8 channels (ANI0 to ANI7) Setting prohibited
Other than above
196
User's Manual U11302EJ4V0UM
CHAPTER 12
A/D CONVERTER
12.4 A/D Converter Operations
12.4.1 Basic operations of A/D converter [1] Set the number of analog input channels using the A/D converter input select register (ADIS). [2] From among the analog input channels set by ADIS, select the channel for A/D conversion using the A/ D converter mode register (ADM). [3] The sample & hold circuit samples the voltage input to the selected analog input channel. [4] Sampling for the specified period of time sets the sample & hold circuit to the hold state so that the circuit holds the input analog voltage until the end of A/D conversion. [5] Bit 7 of the successive approximation register (SAR) is set. The tap selector sets the series resistor string voltage tap to (1/2) AVREF. [6] The voltage difference between the series resistor string voltage tap and analog input is compared by the voltage comparator. If the analog input is larger than (1/2) AVREF, the MSB of the SAR remains set. If the input is smaller than (1/2) AVREF, the MSB is reset. [7] Next, bit 6 of the SAR is automatically set and the operation proceeds to the next comparison. In this case, the series resistor string voltage tap is selected according to the preset value of bit 7 as described below. * Bit 7 = 1: (3/4) AVREF * Bit 7 = 0: (1/4) AVREF The voltage tap and analog input voltage are compared and bit 6 of the SAR is manipulated using the result as follows. * Analog input voltage Voltage tap: Bit 6 = 1 * Analog input voltage < Voltage tap: Bit 6 = 0 [8] Comparison of this sort continues up to bit 0 of the SAR. [9] Upon completion of the comparison of 8 bits, an effective digital result value remains in the SAR and the result value is transferred to and latched in the A/D conversion result register (ADCR). At the same time, the A/D conversion end interrupt request (INTAD) can also be generated.
User's Manual U11302EJ4V0UM
197
CHAPTER 12
A/D CONVERTER
Figure 12-4. Basic Operation of A/D Converter
Conversion time
Sampling time
A/D converter operation
Sampling
A/D conversion
SAR
Undefined
80H
C0H or 40H
Conversion result
ADCR
Conversion result
INTAD
A/D conversion operations are performed continuously until bit 7 (CS) of ADM is reset (0) by software. If a write to ADM is performed during an A/D conversion operation, the conversion operation is initialized, and if CS is set (1), conversion starts again from the beginning. RESET input makes ADCR undefined.
198
User's Manual U11302EJ4V0UM
CHAPTER 12
A/D CONVERTER
12.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/ D conversion result (the value stored in the A/D conversion result register (ADCR)) is shown by the following expression. ADCR = INT( VIN AVREF x 256 + 0.5)
or (ADCR - 0.5) x AVREF 256 VIN < (ADCR + 0.5) x AVREF 256
Remark INT ( ): Function which returns the integer part of the value in parentheses VIN: AVREF: ADCR: Analog input voltage AVREF pin voltage A/D conversion result register (ADCR) value
Figure 12-5 shows the relationship between the analog input voltage and the A/D conversion result. Figure 12-5. Relationship Between Analog Input Voltage and A/D Conversion Result
255
254
253 A/D conversion results (ADCR)
3
2
1
0 1 1 3 2 5 3 512 256 512 256 512 256 507 254 509 255 511 512 256 512 256 512 1
Input voltage/AVREF
User's Manual U11302EJ4V0UM
199
CHAPTER 12
A/D CONVERTER
12.4.3 A/D converter operating mode Select one analog input channel from among ANI0 to ANI7 using the A/D converter input select register (ADIS) and A/D converter mode register (ADM) and start A/D conversion. A/D conversion can be started in the following two ways. * Hardware start: Conversion is started by trigger input (INTP3). * Software start: Conversion is started by setting ADM.
The A/D conversion result is stored in the A/D conversion result register (ADCR) and the interrupt request signal (INTAD) is simultaneously generated. (1) A/D conversion by hardware start When bit 6 (TRG) and bit 7 (CS) of the A/D converter mode register (ADM) are set to 1, the A/D conversion standby state is set. When the external trigger signal (INTP3) is input, A/D conversion starts on the voltage applied to the analog input pins specified by bits 1 to 3 (ADM1 to ADM3) of ADM. At the end of A/D conversion, the conversion result is stored in the A/D conversion result register (ADCR) and the interrupt request signal (INTAD) is generated. After one A/D conversion operation is started and terminated, another operation is not started until a new external trigger signal is input. If data with CS set to 1 is written to ADM again during A/D conversion, the converter suspends its A/D conversion operation and waits for a new external trigger signal to be input. When the external trigger input signal is reinput, A/D conversion is carried out from the beginning. If data with CS set to 0 is written to ADM during A/D conversion, the A/D conversion operation stops immediately. Figure 12-6. A/D Conversion by Hardware Start
INTP3 ADM rewrite CS = 1, TRG = 1 ADM rewrite CS = 1, TRG = 1
A/D conversion
Standby state
ANIn
ANIn
Standby state
ANIn
Standby state
ANIm
ANIm
ANIm
ADCR
ANIn
ANIn
ANIn
ANIm
ANIm
INTAD
Remark
n
= 0, 1, ... , 7
m = 0, 1, ... , 7
200
User's Manual U11302EJ4V0UM
CHAPTER 12
A/D CONVERTER
(2) A/D conversion by software start When bit 6 (TRG) and bit 7 (CS) of the A/D converter mode register (ADM) are set to 0 and 1, respectively, A/D conversion starts on the voltage applied to the analog input pins specified by bits 1 to 3 (ADM1 to ADM3) of ADM. At the end of A/D conversion, the conversion result is stored in the A/D conversion result register (ADCR) and the interrupt request signal (INTAD) is generated. After one A/D conversion operation is started and terminated, the next A/D conversion operation starts immediately. A/D conversion continues repeatedly until new data is written to ADM. If data with CS set to 1 is written to ADM again during A/D conversion, the converter suspends its A/D conversion operation and starts A/D conversion on the newly written data. If data with CS set to 0 is written to ADM during A/D conversion, the A/D conversion operation stops immediately. Figure 12-7. A/D Conversion by Software Start
Conversion start CS = 1, TRG = 0 ADM rewrite CS = 1, TRG = 0 ADM rewrite CS = 0, TRG = 0
A/D conversion
ANIn
ANIn
ANIn
Conversion suspended Conversion results are not stored
ANIm
ANIm
Stop
ADCR
ANIn
ANIn
ANIm
INTAD
Remark
n
= 0, 1, ... , 7
m = 0, 1, ... , 7
User's Manual U11302EJ4V0UM
201
CHAPTER 12
A/D CONVERTER
12.5 A/D Converter Precautions
(1) Power consumption in standby mode The A/D converter operates on the main system clock. Therefore, its operation stops in STOP mode or in HALT mode with the subsystem clock. As a current still flows in the AVREF pin at this time, this current must be cut in order to minimize the overall system power consumption. In this example, the power consumption can be reduced if a low level is output to the output port in the standby mode. However, the actual AVREF voltage is not so accurate and, accordingly, the converted value is not accurate and should be used for relative comparison only. Figure 12-8. Example of Method of Reducing Power Consumption in Standby Mode
VDD
Output port
AVREF AVREF = VDD Series resistor string AVSS
PD780205
202
User's Manual U11302EJ4V0UM
CHAPTER 12
A/D CONVERTER
(2) Input range of ANI0 to ANI7 The input voltages of ANI0 to ANI7 should be within the specification range. In particular, if a voltage greater than or equal to AVREF or less than or equal to AVSS is input (even if within the absolute maximum rating range), the conversion value for that channel will be undefined, and the conversion values of the other channels may also be affected. (3) Noise countermeasures In order to maintain 8-bit resolution, attention must be paid to noise on the AVREF and ANI0 to ANI7 pins. Since the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 12-9 in order to reduce noise. Figure 12-9. Analog Input Pin Processing
If there is possibility that noise whose level is AVREF or higher or AVSS or lower may enter, clamp with a diode with a small VF (0.3 V or less). Reference voltage input AVREF
AVREF ANI0 to ANI7 C = 100 to 1000 pF VDD
AVDD
AVSS
VSS
(4) Pins ANI0/P10 to ANI7/P17 The analog input pins ANI0 to ANI7 also function as I/O port (port 1) pins. Pins used as analog inputs should be set to the input mode. When A/D conversion is performed with any of pins ANI0 to ANI7 selected, be sure not to execute an instruction that inputs data to port 1 while conversion is in progress, as this may reduce the conversion resolution. Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion. (5) AVREF pin input impedance A series resistor string of approximately 10 k is connected between the AVREF pin and the AVSS pin. Therefore, if the output impedance of the reference voltage source is high, this will result in series connection to the series resistor string between the AVREF pin and the AVSS pin, and there will be a large reference voltage error.
User's Manual U11302EJ4V0UM
203
CHAPTER 12
A/D CONVERTER
(6) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the A/D converter mode register (ADM) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result for the analog input before changing and ADIF may be set immediately before rewriting ADM. In this case, if ADIF is read immediately after the rewriting of ADM, ADIF is set despite the fact that A/D conversion of the analog input after changing has not been completed (refer to Figure 12-10). When A/D conversion is stopped, ADIF must be cleared before restarting. Figure 12-10. A/D Conversion End Interrupt Request Generation Timing
ADM rewrite (start of ANIn conversion) ADM rewrite (start of ANIm conversion) ADIF is set but ANIm conversion has not ended
A/D conversion
ANIn
ANIn
ANIm
ANIm
ADCR
ANIn
ANIn
ANIm
ANIm
INTAD
Remark n = 0, 1, ... , 7 m = 0, 1, ... , 7 (7) AVDD pin The AVDD pin is the analog circuit power supply pin, and supplies power to the input circuits of ANI0/P10 to ANI7/P17. Therefore, be sure to apply the voltage at the same level as VDD as shown in Figure 12-11 even in an application where the power supply is switched to the back-up power supply. Figure 12-11. AVDD Pin Connection
AVREF
VDD Main power supply AVDD Back up capacitor VSS AVSS
204
User's Manual U11302EJ4V0UM
CHAPTER 13 SERIAL INTERFACE CHANNEL 0
The PD780208 Subseries incorporates two clocked serial interface channels. The differences between channels 0 and 1 are as follows (refer to CHAPTER 14 SERIAL INTERFACE CHANNEL 1 for details of serial interface channel 1). Table 13-1. Differences Between Channels 0 and 1
Serial Transfer Mode 3-wire serial I/O Clock selection Channel 0 fX/22, fX/23, fX/24, fX/25, fX/26, fX/27, fX/28, fX/29, external clock, TO2 output MSB/LSB switchable as the start bit Channel 1 fX/22, fX/23, fX/24, fX/25, fX/26, fX/27, fX/28, fX/29, external clock, TO2 output MSB/LSB switchable as the start bit Automatic transmit/ receive function Serial transfer end interrupt request flag (CSIIF1) None
Transfer method
Transfer end flag
Serial transfer end interrupt request flag (CSIIF0) Use possible
SBI (serial bus interface) 2-wire serial I/O
User's Manual U11302EJ4V0UM
205
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
13.1 Functions of Serial Interface Channel 0
Serial interface channel 0 has the following four modes. Table 13-2. Modes of Serial Interface Channel 0
Operation Mode Operation stop mode 3-wire serial I/O mode Pins Used - Features * Used when serial transfer is not carried out. * Power consumption can be reduced. * Input and output lines are independent and they can transfer/receive at the same time, so the data transfer processing time is short. * The start bit of 8-bit data to undergo serial transfer is switchable between MSB and LSB. * Enables configuration of serial bus with two signal lines, thus, even when connected to some microcontrollers, the number of ports can be cut and the wiring on the board reduced. * High-speed serial interface complying with the NEC Electronics standard bus format. * Address, command, and data information sent on the serial bus * The wakeup function for handshake and acknowledge and busy signal output function can also be used. * Can cope with any data transfer format by program. Thus, the handshake lines previously necessary for connection of two or more devices can be removed. Usage -
SCK0 (serial clock), SO0 (serial output), SI0 (serial input)
These modes are used for connection of peripheral ICs and display controllers that incorporate a clocked serial interface.
SBI mode
SCK0 (serial clock), SB0 or SB1 (serial data bus)
2-wire serial I/O mode
SCK0 (serial clock), SB0 or SB1 (serial data bus)
Caution
Do not change the operation mode (3-wire serial I/O, 2-wire serial I/O, or SBI) while the operation of serial interface channel 0 is enabled. Stop the serial operation before changing the operation mode.
206
User's Manual U11302EJ4V0UM
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
13.2 Configuration of Serial Interface Channel 0
Serial interface channel 0 consists of the following hardware. Table 13-3. Configuration of Serial Interface Channel 0
Item Registers Configuration Serial I/O shift register 0 (SIO0) Slave address register (SVA) Timer clock select register 3 (TCL3) Serial operating mode register 0 (CSIM0) Serial bus interface control register (SBIC) Interrupt timing specification register (SINT) Port mode register 2 (PM2) Note
Control registers
Note Refer to Figure 4-5 Block Diagram of P20, P21, P23 to P26 and Figure 4-6 Block Diagram of P22 and P27.
User's Manual U11302EJ4V0UM
207
208
Serial operating mode register 0
CSIE0 COI WUP
Figure 13-1. Block Diagram of Serial Interface Channel 0
Internal bus Serial bus interface control register Slave address register (SVA) SVAM Match Controller SI0/SB0/P25 PM25
Output control
User's Manual U11302EJ4V0UM
BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
CSIM CSIM CSIM CSIM CSIM 04 03 02 01 00
Selector P25 output latch Selector
Output control
Serial I/O shift register 0 (SIO0)
CLR SET D Q
CHAPTER 13
SO0/SB1/P26 PM26
P26 output latch
Bus release/ command/ acknowledge detector Serial clock counter
CLD SCK0/P27 PM27
Output control
ACKD CMDD RELD WUP
Busy/ acknowledge output circuit
SERIAL INTERFACE CHANNEL 0
Interrupt request signal generator
INTCSI0 TO2
Serial clock controller CSIM00 CSIM01 P27 output latch
CLD
Selector CSIM00 CSIM01
SIC SVAM
Selector
fX/22 to fX/29
4
TCL33TCL32TCL31TCL30
Interrupt timing specification register Internal bus
Timer clock select register 3
Remark
Output control performs selection between CMOS output and N-ch open-drain output.
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(1) Serial I/O shift register 0 (SIO0) This is an 8-bit register used to carry out parallel/serial conversion and serial transmission/reception (shift operations) in synchronization with the serial clock. SIO0 is set with an 8-bit memory manipulation instruction. When bit 7 (CSIE0) of serial operating mode register 0 (CSIM0) is 1, writing data to SIO0 starts serial operation. In transmission, data written to SIO0 is output to the serial output (SO0) or serial data bus (SB0/SB1). In reception, data is read from the serial input (SI0) or SB0/SB1 to SIO0. The bus configuration in SBI mode and 2-wire serial I/O mode enables the pin to function as both an input and output pin. Thus, when a device is receiving, write FFH to SIO0 in advance (except when address reception is carried out by setting bit 5 (WUP) of CSIM0 to 1). In the SBI mode, the busy state can be cleared by writing data to SIO0. In this case, bit 7 (BSYE) of the serial bus interface control register (SBIC) is not cleared to 0. RESET input makes SIO0 undefined. (2) Slave address register (SVA) This is an 8-bit register used to set the slave address value for connection of a slave device to the serial bus. This register is not used in the 3-wire serial I/O mode. SVA is set with an 8-bit memory manipulation instruction. The master device outputs a slave address to the connected slave devices for selection of a particular slave device. These two data (the slave address output from the master device and the SVA value) are compared by the address comparator. If they match, the slave device has been selected. In that case, bit 6 (COI) of serial operating mode register 0 (CSIM0) becomes 1. Address comparison can also be executed on the data of the LSB-masked higher 7 bits by setting bit 4 (SVAM) of the interrupt timing specification register (SINT) to 1. If no matching is detected in address reception, bit 2 (RELD) of the serial bus interface control register (SBIC) is cleared to 0. The wakeup function can be used by setting bit 5 (WUP) of CSIM0 to 1. In this case, the interrupt request signal (INTCSI0) is generated only when the slave address output by the master matches the value of SVA, and it can be ascertained by this interrupt request that the master is requesting communication. If bit 5 (SIC) of the interrupt timing specification register (SINT) is set to 1, the wakeup function cannot be used even if WUP is set to 1 (an interrupt request signal is generated when bus release is detected). To use the wakeup function, clear SIC to 0. Further, an error can be detected by using SVA when the device transmits data as a master or slave device in the SBI or 2-wire serial I/O mode. RESET input makes SVA undefined. (3) SO0 latch This latch holds the SI0/SB0/P25 and SO0/SB1/P26 pin levels. It can be directly controlled by software. In the SBI mode, this latch is set at the end of the 8th serial clock. (4) Serial clock counter This counter counts the serial clocks to be output and input during transmission/reception and checks whether 8-bit data has been transmitted/received. (5) Serial clock controller This circuit controls serial clock supply to serial I/O shift register 0 (SIO0). When the internal system clock is used, the circuit also controls clock output to the SCK0/P27 pin.
User's Manual U11302EJ4V0UM
209
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(6) Interrupt request signal generator This circuit controls interrupt request signal generation. It generates an interrupt request signal in the following cases. * In the 3-wire serial I/O mode and 2-wire serial I/O mode This circuit generates an interrupt request signal every eight serial clocks. * In the SBI mode When WUPNote is 0 ....... Generates an interrupt request signal every eight serial clocks. When WUPNote is 1 ....... Generates an interrupt request signal when the serial I/O shift register 0 (SIO0) value matches the slave address register (SVA) value after address reception. Note WUP is the wakeup function specification bit. It is bit 5 of serial operating mode register 0 (CSIM0). To use the wakeup function (WUP = 1), clear bit 5 (SIC) of the interrupt timing specification register (SINT) to 0. (7) Busy/acknowledge output circuit and bus release/command/acknowledge detector These two circuits output and detect various control signals in the SBI mode. These do not operate in the 3-wire serial I/O mode and 2-wire serial I/O mode. (8) P27 output latch This latch generates a serial clock by software at the end of eight serial clocks. When using serial interface channel 0, set the P27 output latch to 1. RESET input sets the latch to 0.
210
User's Manual U11302EJ4V0UM
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
13.3 Control Registers of Serial Interface Channel 0
The following four registers are used to control serial interface channel 0. * Timer clock select register 3 (TCL3) * Serial operating mode register 0 (CSIM0) * Serial bus interface control register (SBIC) * Interrupt timing specification register (SINT) (1) Timer clock select register 3 (TCL3) (See Figure 13-2.) This register sets the serial clock of serial interface channel 0. TCL3 is set with an 8-bit memory manipulation instruction. RESET input sets TCL3 to 88H. Remark Besides setting the serial clock of serial interface channel 0, TCL3 sets the serial clock of serial interface channel 1. (2) Serial operating mode register 0 (CSIM0) (See Figure 13-3.) This register sets the serial interface channel 0 serial clock, operating mode, operation enable/stop wakeup function and displays the address comparator match signal. CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H. Caution Do not change the operation mode (3-wire serial I/O, 2-wire serial I/O, or SBI) while the operation of serial interface channel 0 is enabled. Stop the serial operation before changing the operation mode.
User's Manual U11302EJ4V0UM
211
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
Figure 13-2. Format of Timer Clock Select Register 3
Symbol 7 6 5 4 3 2 1 0 Address FF43H After reset 88H R/W R/W
TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30
TCL33 TCL32 TCL31 TCL30 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1
Serial interface channel 0 serial clock selection
2 fX/2 (1.25 MHz) 3 fX/2 (625 kHz)
fX/24 (313 kHz) fX/25 (156 kHz)
6 fX/2 (78.1 kHz)
fX/27 (39.1 kHz) fX/28 (19.5 kHz)
9 fX/2 (9.8 kHz)
Other than above
Setting prohibited
TCL37 TCL36 TCL35 TCL34 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1
Serial interface channel 1 serial clock selection fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.8 kHz) Setting prohibited
Other than above
Caution
If TCL3 is to be rewritten with data other than identical data, stop the serial transfer first.
Remarks 1. fx: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fx = 5.0 MHz.
212
User's Manual U11302EJ4V0UM
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
Figure 13-3. Format of Serial Operating Mode Register 0
Symbol <7> <6> <5> CSIM0 4 3 2 1 0 Address FF60H After reset 00H R/W R/WNote 1
CSIM CSIM CSIM CSIM CSIM CSIE0 COI WUP 04 03 02 01 00
R/W CSIM CSIM 01 00 0 1 1 x 0 1
Serial interface channel 0 clock selection Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) Operating mode 3-wire serial I/O mode Start bit MSB LSB
Note 3 Note 3
R/W CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 04 03 02 0 0 x 1 1 x 0 0 0 1
SI0/P25 pin function SI0 Note 2 (input)
SO0/P26 pin function SO0 (CMOS output)
SCK0/P27 pin function SCK0 (CMOS I/O)
SBI mode 0 0 0 1
MSB
0 1 0
x
x
P25 (CMOS I/O)
SB1 (N-ch open-drain I/O) P26 (CMOS I/O)
SCK0 (CMOS I/O)
Note 3 Note 3
1
0
0
x
x
0
1
SB0 (N-ch open-drain I/O) 2-wire serial I/O mode MSB P25 (CMOS I/O)
Note 3 Note 3
0 1 1
x
x
0
0
0
1
SB1 SCK0 (N-ch open-drain (N-ch open-drain I/O) I/O) P26 (CMOS I/O)
Note 3 Note 3
1
0
0
x
x
0
1
SB0 (N-ch open-drain I/O)
R/W WUP 0 1
Wakeup function control Note 4 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1) matches the slave address register (SVA) in SBI mode
R
COI 0 1
Slave address comparison result flag Note 5 Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data
R/W CSIE0 Serial interface channel 0 operation control 0 1 Operation stopped Operation enabled
Notes 1. 2. 3. 4.
Bit 6 (COI) is a read-only bit. Can be used as P25 (CMOS input) when used only for transmission. Can be used freely as port function. To use the wakeup function (WUP = 1), clear bit 5 (SIC) of the interrupt timing specification register (SINT) to 0. 5. COI becomes 0 when CSIE0 = 0. x: don't care PMxx: Port mode register Pxx: Port output latch
User's Manual U11302EJ4V0UM
Remark
213
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(3) Serial bus interface control register (SBIC) This register sets the serial bus interface operation and displays statuses. SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H. Figure 13-4. Format of Serial Bus Interface Control Register (1/2)
Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address FF61H After reset 00H R/W R/WNote
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
R/W
RELT
Used for bus release signal output. When RELT = 1, the SO latch is set to 1. After SO latch setting, RELT is automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
R/W
CMDT
Used for command signal output. When CMDT = 1, the SO latch is cleared to 0. After SO latch clearance, CMDT is automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
R
RELD
Bus release detection Set conditions (RELD = 1) * When bus release signal (REL) is detected
Clear conditions (RELD = 0) * When transfer start instruction is executed * If SIO0 and SVA values do not match in address reception * When CSIE0 = 0 * When RESET input is applied
R
CMDD
Command detection Set conditions (CMDD = 1) * When command signal (CMD) is detected
Clear conditions (CMDD = 0) * * * * When When When When transfer start instruction is executed bus release signal (REL) is detected CSIE0 = 0 RESET input is applied
R/W
ACKT
The acknowledge signal is output in synchronization with the falling edge clock of SCK0 just after execution of the instruction to be set to 1, and after acknowledge signal output, ACKT is automatically cleared to 0. Also cleared to 0 upon start of serial interface transfer or when CSIE0 = 0.
Note Bits 2, 3, and 6 (RELD, CMDD, and ACKD) are read-only bits. Remark CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
214
User's Manual U11302EJ4V0UM
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
Figure 13-4. Format of Serial Bus Interface Control Register (2/2)
R/W
ACKE 0
Acknowledge signal output control Acknowledge signal automatic output disabled (output with ACKT enabled) Before completion of transfer The acknowledge signal is output in synchronization with the 9th clock falling edge of SCK0 (automatically output when ACKE = 1). The acknowledge signal is output in synchronization with the falling edge of SCK0 just after execution of the instruction to be set to 1 (automatically output when ACKE = 1). However, ACKE is not automatically cleared to 0 after acknowledge signal output.
1
After completion of transfer
R
ACKD
Acknowledge detection Set conditions (ACKD = 1) * When acknowledge signal (ACK) is detected at the rising edge of SCK0 clock after completion of transfer
Clear conditions (ACKD = 0) * At the falling edge of SCK0 immediately after the busy mode has been released when a transfer start instruction is executed * When CSIE0 = 0 * When RESET input is applied
R/W BSYENote Synchronizing busy signal output control 0 1 Busy signal which is output in synchronization with the falling edge of SCK0 clock just after execution of the instruction to be cleared to 0 is disabled. Busy signal is output at the falling edge of SCK0 clock following the acknowledge signal.
Note
Busy mode can be cleared by start of serial interface transfer. However, the BSYE flag is not cleared to 0.
Remarks
1. Bits 0, 1, and 4 (RELT, CMDT, and ACKT) are 0 when read after data setting. 2. CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
User's Manual U11302EJ4V0UM
215
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(4) Interrupt timing specification register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0 pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H. Figure 13-5. Format of Interrupt Timing Specification Register
Symbol SINT 7 0 <6> CLD <5> <4> 3 0 2 0 1 0 0 0 Address FF63H After reset 00H R/W R/WNote 1
SIC SVAM
R/W
SVAM 0 1
SVA bit to be used as slave address Bits 0 to 7 Bits 1 to 7
R/W
SIC 0 1
INTCSI0 interrupt source selectionNote 2 CSIIF0 is set upon termination of serial interface channel 0 transfer CSIIF0 is set upon bus release detection or termination of serial interface channel 0 transfer
R
CLD 0 1
SCK0 pin levelNote 3 Low level High level
Notes 1. Bit 6 (CLD) is a read-only bit. 2. When using wakeup function, set SIC to 0. 3. When CSIE0 = 0, CLD becomes 0. Caution Be sure to set bits 0 to 3 to 0. Remark SVA: CSIE0: Slave address register Bit 7 of serial operating mode register 0 (CSIM0)
CSIIF0: Interrupt request flag for INTCSI0
216
User's Manual U11302EJ4V0UM
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
13.4 Operations of Serial Interface Channel 0
The following four operating modes are available for serial interface channel 0. * Operation stop mode * 3-wire serial I/O mode * SBI mode * 2-wire serial I/O mode 13.4.1 Operation stop mode Serial transfer is not carried out in the operation stop mode. Thus, power consumption can be reduced. Serial I/O shift register 0 (SIO0) does not carry out shift operations and can be used as an ordinary 8-bit register. In the operation stop mode, the P25/SI0/SB0, P26/SO0/SB1, and P27/SCK0 pins can be used as ordinary I/O ports. (1) Register setting The operation stop mode is set by serial operating mode register 0 (CSIM0). CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H.
Symbol <7> <6> <5> WUP 4 3 2 1 0 Address FF60H After reset 00H R/W R/W
CSIM0 CSIE0 COI
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
R/W
CSIE0 0 1
Serial interface channel 0 operation control Operation stopped Operation enabled
User's Manual U11302EJ4V0UM
217
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
13.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is used for connection of peripheral ICs and display controllers that incorporate a clocked serial interface. Communication is carried out using three lines: a serial clock (SCK0), serial output (SO0), and serial input (SI0). (1) Register setting The 3-wire serial I/O mode is set by serial operating mode register 0 (CSIM0) and serial bus interface control register (SBIC). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H.
218
User's Manual U11302EJ4V0UM
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
Symbol <7> <6> <5> CSIM0 4 3 2 1 0 Address FF60H After reset 00H R/W R/WNote 1
CSIM CSIM CSIM CSIM CSIM CSIE0 COI WUP 04 03 02 01 00
R/W
CSIM CSIM 01 00 0 1 1 x 0 1
Serial interface channel 0 clock selection Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
R/W
CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 04 03 02 0 0 x 1 1 1 0 1 1 x 0 0 0 1
Operating mode 3-wire serial I/O mode
Start bit MSB LSB
SI0/P25 pin function SI0Note 2 (input)
SO0/P26 pin function SO0 (CMOS output)
SCK0/P27 pin function SCK0 (CMOS I/O)
SBI mode (refer to 13.4.3 SBI mode operation) 2-wire serial I/O mode (refer to 13.4.4 2-wire serial I/O mode operation)
R/W
WUP 0 1
Wakeup function control Note 3 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1) matches the slave address register (SVA) in SBI mode
R
COI 0 1
Slave address comparison result flag Note 4 Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data
R/W CSIE0 Serial interface channel 0 operation control 0 1 Operation stopped Operation enabled
Notes 1. Bit 6 (COI) is a read-only bit. 2. Can be used as P25 (CMOS input) when used only for transmission. 3. Set WUP to 0 when the 3-wire serial I/O mode is selected. 4. When CSIE0 = 0, COI becomes 0. Remark x: Pxx: don't care Port output latch
PMxx: Port mode register
User's Manual U11302EJ4V0UM
219
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H.
Symbol
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
Address FF61H
After reset 00H
R/W R/W
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
R/W
RELT
When RELT = 1, the SO latch is set to 1. After SO latch setting, RELT is automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
R/W
CMDT
When CMDT = 1, the SO latch is cleared to 0. After SO latch clearance, CMDT is automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
220
User's Manual U11302EJ4V0UM
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/ reception is carried out bit by bit in synchronization with the serial clock. Shift operations of serial I/O shift register 0 (SIO0) are carried out at the falling edge of the serial clock (SCK0). The transmit data is held in the SO0 latch and is output from the SO0 pin. The receive data input to the SI0 pin is latched into SIO0 at the rising edge of SCK0. Upon termination of 8-bit transfer, SIO0 operation stops automatically and the interrupt request flag (CSIIF0) is set. Figure 13-6. 3-Wire Serial I/O Mode Timing
SCK0
1
2
3
4
5
6
7
8
SI0
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
CSIIF0 End of transfer Transfer start at falling edge of SCK0
The SO0 pin is used for CMOS output and generates the SO0 latch status. Thus, the SO0 pin output status can be manipulated by setting bit 0 (RELT) and bit 1 (CMDT) of the serial bus interface control register (SBIC). However, do not carry out this manipulation during serial transfer. Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27 output latch (refer to 13.4.5 SCK0/P27 pin output manipulation).
User's Manual U11302EJ4V0UM
221
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(3) Signals Figure 13-7 shows the RELT and CMDT operations. Figure 13-7. RELT and CMDT Operations
SO0 latch
RELT
CMDT
(4) MSB/LSB switching as the start bit In the 3-wire serial I/O mode, transfer can be selected to start from the MSB or LSB. Figure 13-8 shows the configuration of serial I/O shift register 0 (SIO0) and the internal bus. As shown in the figure, the MSB/LSB can be read/written in reverse form. MSB/LSB switching as the start bit can be specified using bit 2 (CSIM02) of serial operating mode register 0 (CSIM0). Figure 13-8. Circuit for Switching Transfer Bit Order
7 6 Internal bus 1 0 LSB start MSB start Read/write gate Read/write gate
SO0 latch SI0 Shift register 0 (SIO0) D Q
SO0
SCK0
Start bit switching is realized by switching the bit order for data write to SIO0. The SIO0 shift order remains unchanged. Thus, switch the MSB/LSB start bit before writing data to the shift register.
222
User's Manual U11302EJ4V0UM
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(5) Transfer start Serial transfer is started by setting transfer data to serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. * Serial interface channel 0 operation control bit (CSIE0) = 1 * Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer. Caution If CSIE0 is set to "1" after data write to SIO0, transfer does not start. Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0) is set. 13.4.3 SBI mode operation SBI (Serial Bus Interface) is a high-speed serial interface that complies with the NEC Electronics serial bus format. SBI is a single-master high-speed serial bus with a format in which a bus configuration function has been added to the clocked serial I/O method so that it can carry out communication with two or more devices using two signal lines. Thus, when configuring a serial bus with two or more microcontrollers or peripheral ICs, the number of ports to be used and the number of wires on the board can be decreased. The master device can output to the serial data bus of the slave device "addresses" for selection of the serial communication target device, "commands" to instruct the target device and actual "data". The slave device can identify the received data as an "address", "command", or "data", by hardware. This function can simplify the application program which controls serial interface channel 0. The SBI function is incorporated into various devices including the 75XL Series and 78K Series. Figure 13-9 shows a serial bus configuration example when a CPU having a serial interface compliant with SBI and peripheral ICs are used. In SBI, the SB0 (SB1) serial data bus pin is an open-drain output and so the serial data bus line is in a wiredOR state. A pull-up resistor is therefore necessary for the serial data bus line. Refer to (11) SBI mode precautions (d) described later when the SBI mode is used.
User's Manual U11302EJ4V0UM
223
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
Figure 13-9. Example of Serial Bus Configuration with SBI
VDD
Serial clock SCK0 Master CPU Serial data bus SB0 (SB1) SB0 (SB1) Address 1 SCK0 Slave CPU
SCK0
Slave CPU
SB0 (SB1)
Address 2
SCK0
***
Slave IC
SB0 (SB1)
Address N
Caution
When replacing the master CPU/slave CPU, a pull-up resistor is necessary for the serial clock line (SCK0) as well because serial clock line (SCK0) input/output switching is carried out asynchronously between the master and slave CPUs.
224
User's Manual U11302EJ4V0UM
***
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(1) SBI functions With the conventional serial I/O method, when a serial bus is configured by connecting two or more devices, many ports and wiring are necessary to distinguish chip select signals and command/data and to judge the busy state because only a data transfer function is available. Controlling these operations by software places a heavy load on the software. In SBI, a serial bus can be configured with two signal lines: a serial clock SCK0 and serial data bus SB0 (SB1). Thus, SBI is effective to decrease the number of microcontroller ports and wiring and routing on the board. The SBI functions are described below. (a) Address/command/data identification function Serial data is distinguished into addresses, commands, and data. (b) Chip select function by address transmission The master executes slave chip selection by address transmission. (c) Wakeup function The slave can easily judge address reception (chip select judgment) using the wakeup function (which can be set/reset by software). When the wakeup function is set, the interrupt request signal (CSIIF0) is generated upon reception of a match address. Thus, when communication is executed with two or more devices, the CPUs of other than the selected slave device can operate irrespective of serial communication. (d) Acknowledge signal (ACK) control function The acknowledge signal to check serial data reception is controlled. (e) Busy signal (BUSY) control function The busy signal to report the slave busy state is controlled.
User's Manual U11302EJ4V0UM
225
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(2) SBI definition The SBI serial data format is defined as follows. Serial data to be transferred with SBI is distinguished into three types, "address", "command", and "data". Figure 13-10 shows the address, command, and data transfer timing. Figure 13-10. SBI Transfer Timing
Address transfer
SCK0
8
9
SB0/SB1 Bus release signal
A7 Address
A0
ACK
BUSY
Command transfer
Command signal 9
SCK0
SB0/SB1
C7 Command
C0 ACK
BUSY
READY
Data transfer
SCK0
8
9
SB0/SB1
D7 Data
D0 ACK
BUSY
READY
Remark
The broken line indicates the READY status.
The bus release signal and the command signal are output by the master device. BUSY is output by the slave. ACK can be output by either the master or slave device (normally, the 8-bit data receiver outputs ACK). Serial clocks continue to be output by the master device from 8-bit data transfer start to BUSY reset.
226
User's Manual U11302EJ4V0UM
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(a) Bus release signal (REL) The bus release signal is identified when the SB0 (SB1) line has changed from low level to high level while the SCK0 line is high level (without serial clock output). This signal is output by the master device. Figure 13-11. Bus Release Signal
SCK0 SB0 (SB1)
"H"
The bus release signal indicates that the master device is going to transmit an address to the slave device. The slave device incorporates hardware to detect the bus release signal. Caution If the SB0 (SB1) line changes from low level to high level while the SCK0 line is high level, it is recognized as a bus release signal. Therefore, if the changing timing of the bus fluctuates because of substrate capacitance, etc., it may be recognized as a bus release signal even while data is being transmitted. Care should therefore be taken in the wiring. (b) Command signal (CMD) The command signal is identified when the SB0 (SB1) line has changed from high level to low level while the SCK0 line is high level (without serial clock output). This signal is output by the master device. Figure 13-12. Command Signal
SCK0 SB0 (SB1)
"H"
The command signal indicates that from this point, the master will send a command to the slave (however, command signals following bus release signals indicate that an address will be sent). The slave incorporates hardware to detect command signals. Caution If the SB0 (SB1) line changes from high level to low level while the SCK0 line is high level, it is recognized as a command signal. Therefore, if the changing timing of the bus fluctuates because of substrate capacitance, etc., it may be recognized as a command signal even while data is being transmitted. Care should therefore be taken in the wiring.
User's Manual U11302EJ4V0UM
227
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(c) Address An address is 8-bit data which the master device outputs to the slave device connected to the bus line in order to select a particular slave device. Figure 13-13. Address
SCK0 SB0 (SB1) 1 A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 A0
Address Bus release signal Command signal
8-bit data following bus release and command signals is defined as an "address". In the slave device, this condition is detected by hardware and whether or not the 8-bit data matches the slave's own specification number (slave address) is checked by hardware. If the 8-bit data matches the slave address, the slave device has been selected. After that, communication with the master device continues until a release instruction is received from the master device. Figure 13-14. Slave Selection by Address
Master Slave 2 address transmission
Slave 1
Not selected
Slave 2
Selected
Slave 3
Not selected
Slave 4
Not selected
228
User's Manual U11302EJ4V0UM
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(d) Command and data The master device transmits commands to, and transmits/receives data to/from the slave device selected by address transmission. Figure 13-15. Commands
SCK0 SB0 (SB1)
1 C7
2 C6
3 C5
4 C4
5 C3
6 C2
7 C1
8 C0
Command signal
Command
Figure 13-16. Data
SCK0 SB0 (SB1) 1 D7 2 D6 3 D5 4 D4 Data 5 D3 6 D2 7 D1 8 D0
8-bit data following a command signal is defined as "command" data. 8-bit data without a command signal is defined as "data". Command and data operation procedures can be determined by the user according to their communication specifications.
User's Manual U11302EJ4V0UM
229
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(e) Acknowledge signal (ACK) The acknowledge signal is used to check serial data reception between the transmitter and receiver. Figure 13-17. Acknowledge Signal [When output in synchronization with 11th clock of SCK0]
SCK0 8 9 10 11
SB0 (SB1)
ACK
[When output in synchronization with 9th clock of SCK0]
SCK0 8 9
SB0 (SB1)
ACK
Remark
The broken line indicates the READY status.
The acknowledge signal is a one-shot pulse generated at the falling edge of SCK0 after 8-bit data transfer. It can be positioned anywhere and can be synchronized with any clock of SCK0. After 8-bit data transmission, the transmitter checks whether the receiver has returned the acknowledge signal. If the acknowledge signal is not returned for the preset period of time after data transmission, it can be judged that data reception has not been carried out correctly.
230
User's Manual U11302EJ4V0UM
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(f) Busy signal (BUSY) and ready signal (READY) The BUSY signal is used to report to the master device that the slave device is not ready for data transmission/reception. The READY signal is used to report to the master device that the slave device is ready for data transmission/reception. Figure 13-18. BUSY and READY Signals
SCK0 8 9
SB0 (SB1)
ACK
BUSY
READY
In SBI, the slave device notifies the master device of the busy state by setting the SB0 (SB1) line to low level. BUSY signal output follows acknowledge signal output from the master or slave device. It is set/reset at the falling edge of SCK0. When the BUSY signal is reset, the master device automatically terminates the output of the SCK0 serial clock. When the BUSY signal is reset and the READY signal is set, the master device can start the next transfer. Caution In SBI, after specifying reset of BUSY, the BUSY signal is output until the fall of the next serial clock (SCK0). If WUP = 1 is set during this interval by mistake, it will be impossible to reset BUSY. Therefore, after BUSY is released, make sure that the SB0 (SB1) pin is high level before setting WUP = 1. (3) Register setting The SBI mode is set by serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specification register (SINT).
User's Manual U11302EJ4V0UM
231
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H.
Symbol <7> <6> <5> CSIM0 4 3 2 1 0 Address FF60H After reset 00H R/W R/WNote 1
CSIM CSIM CSIM CSIM CSIM CSIE0 COI WUP 04 03 02 01 00
R/W
CSIM CSIM 01 00 0 1 1 x 0 1
Serial interface channel 0 clock selection Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
R/W CSIM CSIM CSIM 04 03 02 PM25 P25 PM26 P26 PM27 P27 0 x
Operating mode
Start bit
SI0/P25 pin function
SO0/P26 pin function
SCK0/P27 pin function
3-wire serial I/O mode (refer to 13.4.2 3-wire serial I/O mode operation)
Note 2 Note 2
SBI mode 0 0 0 1
MSB
0 1 0
x
x
P25 (CMOS I/O)
SB1 (N-ch open-drain I/O) P26 (CMOS I/O)
SCK0 (CMOS I/O)
Note 2 Note 2
1
0
0
x
x
0
1
SB0 (N-ch open-drain I/O)
1
1
2-wire serial I/O mode (refer to 13.4.4 2-wire serial I/O mode operation)
R/W
WUP 0 1
Wakeup function control Note 3 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1) matches the slave address register (SVA) in SBI mode
R
COI 0 1
Slave address comparison result flag Note 4 Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data
R/W CSIE0 Serial interface channel 0 operation control 0 1 Operation stopped Operation enabled
Notes 1. Bit 6 (COI) is a read-only bit. 2. Can be used freely as port function. 3. To use the wakeup function (WUP = 1), clear bit 5 (SIC) of the interrupt timing specification register (SINT) to 0. 4. When CSIE0 = 0, COI becomes 0. Remark x: don't care PMxx: Port mode register Pxx: Port output latch
User's Manual U11302EJ4V0UM
232
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H.
Symbol
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
Address FF61H
After reset 00H
R/W R/WNote
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
R/W
RELT
Used for bus release signal output. When RELT = 1, the SO latch is set to 1. After SO latch setting, RELT is automatically cleared to 0. Also cleared to 0 when CSIE0 = 0. Used for command signal output. When CMDT = 1, the SO latch is cleared to 0. After SO latch clearance, CMDT is automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
R/W
CMDT
R
RELD
Bus release detection Set conditions (RELD = 1) * When bus release signal (REL) is detected
Clear conditions (RELD = 0) * When transfer start instruction is executed * If SIO0 and SVA values do not match in address reception * When CSIE0 = 0 * When RESET input is applied
R
CMDD
Command detection Set conditions (CMDD = 1) * When command signal (CMD) is detected
Clear conditions (CMDD = 0) * * * * R/W When When When When transfer start instruction is executed bus release signal (REL) is detected CSIE0 = 0 RESET input is applied
ACKT
The acknowledge signal is output in synchronization with the falling edge clock of SCK0 just after execution of the instruction to be set to 1, and after acknowledge signal output, ACKT is automatically cleared to 0. Used as ACKE = 0. Also cleared to 0 upon start of serial interface transfer or when CSIE0 = 0. (continued)
Note
Bits 2, 3, and 6 (RELD, CMDD, and ACKD) are read-only bits. 1. Bits 0, 1, and 4 (RELT, CMDT, and ACKT) are 0 when read after data setting. 2. CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
Remarks
User's Manual U11302EJ4V0UM
233
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(continued) R/W ACKE 0 Acknowledge signal output control Acknowledge signal automatic output disabled (output with ACKT enabled) Before completion of transfer 1 After completion of transfer The acknowledge signal is output in synchronization with the 9th clock falling edge of SCK0 (automatically output when ACKE = 1). The acknowledge signal is output in synchronization with the falling edge of SCK0 just after execution of the instruction to be set to 1 (automatically output when ACKE = 1). However, ACKE is not automatically cleared to 0 after acknowledge signal output.
R
ACKD
Acknowledge detection Set conditions (ACKD = 1)
Clear conditions (ACKD = 0)
* At the falling edge of SCK0 immediately after the * When acknowledge signal (ACK) is detected at the busy mode has been released when a transfer start rising edge of SCK0 clock after completion of instruction is executed transfer * When CSIE0 = 0 * When RESET input is applied
R/W
BSYENote Synchronizing busy signal output control 0 1 Busy signal which is output in synchronization with the falling edge of SCK0 clock just after execution of the instruction to be cleared to 0 (sets ready state) is disabled. Busy signal is output at the falling edge of SCK0 clock following the acknowledge signal.
Note
Busy mode can be cleared by start of serial interface transfer. However, the BSYE flag is not cleared to 0.
Remark CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
234
User's Manual U11302EJ4V0UM
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(c) Interrupt timing specification register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H.
Symbol SINT 7 0 <6> CLD <5> <4> 3 0 2 0 1 0 0 0 Address FF63H After reset 00H R/W R/WNote 1
SIC SVAM
R/W SVAM 0 1 R/W SIC 0 1 SVA bit to be used as slave address Bits 0 to 7 Bits 1 to 7
INTCSI0 interrupt source selectionNote 2 CSIIF0 is set upon termination of serial interface channel 0 transfer CSIIF0 is set upon bus release detection or termination of serial interface channel 0 transfer
R CLD 0 1
SCK0 pin levelNote 3 Low level High level
Notes 1. Bit 6 (CLD) is a read-only bit. 2. When using the wakeup function in the SBI mode, set SIC to 0. 3. When CSIE0 = 0, CLD becomes 0. Caution Be sure to set bits 0 to 3 to 0. Remark SVA: Slave address register
CSIIF0: Interrupt request flag for INTCSI0 CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
User's Manual U11302EJ4V0UM
235
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(4) Signals Figures 13-19 to 13-24 show the signals and operations of the flags of the serial bus interface control register (SBIC) in SBI. Table 13-4 lists the signals in SBI. Figure 13-19. RELT, CMDT, RELD, and CMDD Operations (Master)
Slave address write to SIO0 (transfer start instruction) SIO0
SCK0 SB0 (SB1)
RELT
CMDT RELD
CMDD
Figure 13-20. RELD and CMDD Operations (Slave)
Write FFH to SIO0 (transfer start instruction)
Transfer start instruction
SIO0
A7
A6
A1
A0
SCK0
1
2
7
8
9 READY
SO0 latch
A7
A6
A1
A0
ACK
Slave address When addresses match RELD When addresses do not match CMDD
236
User's Manual U11302EJ4V0UM
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
Figure 13-21. ACKT Operation
SCK0 SB0/SB1 ACKT
6 D2
7 D1
8 D0
9 ACK ACK signal is output for a period of one clock just after setting
When set during this period
Caution Do not set ACKT before termination of transfer.
User's Manual U11302EJ4V0UM
237
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
Figure 13-22. ACKE Operations (a) When ACKE = 1 upon completion of transfer
SCK0 1 2 7 8 9
SB0/SB1 ACKE
D7
D6
D2
D1
D0
ACK
ACK signal is output at 9th clock
When ACKE = 1 at this point
(b) When set after completion of transfer
SCK0 6 7 8 9
SB0/SB1
D2
D1
D0
ACK
ACK signal is output for a period of one clock just after setting
ACKE
If set during this period and ACKE = 1 at the falling edge of the next SCK0
(c) When ACKE = 0 upon completion of transfer
SCK0 SB0/SB1 1 D7 2 D6 D2 7 D1 8 D0 9 ACK signal is not output
ACKE
When ACKE = 0 at this point
(d) When ACKE = 1 period is short
SCK0 SB0/SB1 D2 D1 D0 ACK signal is not output
ACKE
If set and cleared during this period and ACKE = 0 at the falling edge of SCK0
238
User's Manual U11302EJ4V0UM
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
Figure 13-23. ACKD Operations (a) When ACK signal is output at 9th clock of SCK0
Transfer start instruction SIO0 Transfer start SCK0 SB0/SB1 6 7 8 9
D2
D1
D0
ACK
ACKD
(b) When ACK signal is output after 9th clock of SCK0
Transfer start instruction SIO0 Transfer start SCK0 SB0/SB1 6 7 8 9
D2
D1
D0
ACK
ACKD
(c) Clear timing when transfer start is instructed during BUSY
Transfer start instruction SIO0
SCK0 SB0/SB1
6
7
8
9
ACK
D2
D1
D0
BUSY
D7
D6
ACKD
Figure 13-24. BSYE Operation
6 7 8 9
SCK0
SB0/SB1
D2
D1
D0
ACK
BUSY
BSYE
When BSYE = 1 at this point
If reset during this period and BSYE = 0 at the falling edge of SCK0
User's Manual U11302EJ4V0UM
239
240
Signal Name Output Device Master Definition Bus release signal (REL) SB0/SB1 rising edge when SCK0 = 1 Command signal (CMD) Master SB0/SB1 falling edge when SCK0 = 1
User's Manual U11302EJ4V0UM
Table 13-4. Signals in SBI Mode (1/2)
Timing Chart
Output Condition
Effect on Flag
Meaning of Signal
* RELT set
SCK0 SB0/SB1 "H"
* RELD set * CMDD clear
CMD signal is output to indicate that transmit data is an address. i) Transmit data is an address after REL signal output. ii) REL signal is not output and transmit data is a command.
* CMDT set
SCK0 SB0/SB1 "H"
* CMDD set
CHAPTER 13 SERIAL INTERFACE CHANNEL 0
Acknowledge signal (ACK)
Master/ slave
Low-level signal output to SB0/SB1 during one-clock period of SCK0 after completion of serial reception [Synchronous BUSY output] [Synchronous BUSY signal] Low-level signal output to SB0/SB1 following acknowledge signal
[1] ACKE = 1 [2] ACKT set
* ACKD set
Completion of reception
Busy signal (BUSY)
Slave
* BSYE = 1
--
SCK0 SB0/SB1 D0
9
ACK BUSY
Serial receive disabled because of processing
READY
ACK BUSY
Ready signal (READY)
Slave
High-level signal output to SB0/SB1 before serial transfer start and after completion of serial transfer
SB0/SB1 D0
READY
[1] BSYE = 0 [2] Execution of instruction data write to SIO0 (transfer start instruction)
--
Serial receive enabled
Table 13-4. Signals in SBI Mode (2/2)
Output Device Master
Signal Name
Definition
Timing Chart
Output Condition
Effect on Flag
Meaning of Signal
Serial clock (SCK0)
Synchronous clock to output address/command/data, ACK signal, synchronous BUSY signal, etc. Address/command/data are transferred with the first eight synchronous clocks. 8-bit data transferred in synchronization with SCK0 after output of REL and CMD signals
SCK0 SB0/SB1
1
2
7
8
9
10
Address (A7 to A0)
User's Manual U11302EJ4V0UM
Master
SCK0 SB0/SB1
1
2
7
8
When CSIE0 = 1, CSIIF0 set (rising Timing of signal edge of 9th clock output to serial data execution of of SCK0)Note 1 instruction for bus data write to SIO0 (serial transfer start instruction)Note 2 Address value of slave device on the serial bus
CHAPTER 13 SERIAL INTERFACE CHANNEL 0
REL CMD
Command (C7 to C0)
Master
8-bit data transferred in synchronization with SCK0 after output of only CMD signal without REL signal output
SCK0 SB0/SB1
1
2
7
8
Instructions and messages to the slave device
CMD
Data (D7 to D0)
Master/ slave
8-bit data transferred in synchronization with SCK0 without output of REL and CMD signals
SCK0 SB0/SB1
1
2
7
8
Numeric values to be processed with slave or master device
Notes 1. When WUP = 0, CSIIF0 is always set at the rising edge of the 9th clock of SCK0. When WUP = 1, CSIIF0 is set only when the received address matches the slave address register (SVA) value. 2. In the BUSY state, transfer starts after the READY state is entered.
241
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(5) Pin configuration The serial clock pin SCK0 and serial data bus pin SB0 (SB1) have the following configurations. (a) SCK0: [2] Slave: Serial clock I/O pin Schmitt input Both master and slave devices have an N-ch open-drain output and a Schmitt input. Because the serial data bus line has an N-ch open-drain output, an external pull-up resistor is necessary. Figure 13-25. Pin Configuration
Slave device
[1] Master: CMOS and push-pull output (b) SB0 (SB1): Serial data I/O alternate-function pin
Master device (Clock output) Clock input Serial clock (Clock input) VDD N-ch open-drain SO0 SB0 (SB1) RL Serial data bus SB0 (SB1) N-ch open-drain SO0
SCK0 Clock output
SCK0
SI0
SI0
Caution
Because the N-ch open-drain output must be high impedance at the time of data reception, write FFH to serial I/O shift register 0 (SIO0) in advance. The N-ch opendrain output can be high impedance throughout transfer. However, when the wakeup function specification bit (WUP) = 1, the N-ch open-drain output is always high impedance. Thus, it is not necessary to write FFH to SIO0.
242
User's Manual U11302EJ4V0UM
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(6) Address match detection method In the SBI mode, the master transmits a slave address to select a specific slave device. A match of the addresses can be automatically detected by hardware. CSIIF0 is set only when the slave address transmitted by the master matches the address set to SVA when the wakeup function specification bit (WUP) = 1. If bit 5 (SIC) of the interrupt timing specification register (SINT) is set to 1, the wakeup function cannot be used even if WUP is set to 1 (an interrupt request signal is generated when bus release is detected). To use the wakeup function, clear SIC to 0. Cautions 1. Slave selection/non-selection is detected by matching of the slave address received after bus release (RELD = 1). For this match detection, the match interrupt request (CSIIF0) of the address to be generated with WUP = 1 is normally used. Thus, execute selection/non-selection detection by slave address when WUP = 1. 2. When detecting selection/non-selection without the use of an interrupt request with WUP = 0, do so by means of transmission/reception of the command preset by program instead of using the address match detection method. (7) Error detection In the SBI mode, the serial bus SB0 (SB1) status being transmitted is fetched into the destination device, that is, serial I/O shift register 0 (SIO0). Thus, transmit errors can be detected in the following two ways. (a) Comparison of SIO0 data before transmission to that after transmission In this case, if the two data differ, a transmit error is judged to have occurred. (b) Use of the slave address register (SVA) Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, the COI bit (match signal coming from the address comparator) of serial operating mode register 0 (CSIM0) is tested. If "1", normal transmission is judged to have been carried out. If "0", a transmit error is judged to have occurred. (8) Communication operation In the SBI mode, the master device normally selects one slave device as the communication target from among two or more devices by outputting an "address" to the serial bus. After the communication target device has been determined, commands and data are transmitted/ received and serial communication is realized between the master and slave devices. Figures 13-26 to 13-29 show data communication timing charts. Shift operations of serial I/O shift register 0 (SIO0) are carried out at the falling edge of the serial clock (SCK0). Transmit data is latched into the SO0 latch and is output with the MSB set as the start bit from the SB0/P25 or SB1/P26 pin. Receive data input to the SB0 (or SB1) pin at the rising edge of SCK0 is latched into SIO0.
User's Manual U11302EJ4V0UM
243
244
Master device processing (transmitter) Transfer line
User's Manual U11302EJ4V0UM
Figure 13-26. Address Transmission from Master Device to Slave Device (WUP = 1)
Program processing
CMDT set
RELT set
CMDT set
Write to SIO0
Interrupt servicing (preparation for the next serial transfer)
Hardware operation
Serial transmission
INTCSI0
generation
ACKD
set
SCK0
stop
CHAPTER 13
SCK0 pin
1
2
3
4
5
6
7
8
9
SERIAL INTERFACE CHANNEL 0
SB0 pin
A7
A6
A5
A4
A3
A2
A1
A0
ACK
BUSY
READY
Address Slave device processing (receiver) Program processing
WUP0 ACKT set
BUSY
clear
Hardware operation
CMDD CMDD CMDD set clear set RELD set
Serial reception
INTCSI0
generation
ACK BUSY
output output
BUSY
clear
(When SVA = SIO0)
Figure 13-27. Command Transmission from Master Device to Slave Device
Master device processing (transmitter) Program processing
CMDT set Write to SIO0
Interrupt servicing (preparation for the next serial transfer)
Hardware operation
Serial transmission
INTCSI0
generation
ACKD
set
SCK0
stop
CHAPTER 13
Transfer line SCK0 pin 1 2 3 4 5 6 7 8 9
User's Manual U11302EJ4V0UM
SERIAL INTERFACE CHANNEL 0
SB0 pin
C7
C6
C5
C4
C3
C2
C1
C0
ACK
BUSY
READY
Command Slave device processing (receiver) Program processing
SIO0 read
Command ACKT analysis set
BUSY
clear
Hardware operation
CMDD set
Serial reception
INTCSI0
generation
ACK BUSY
output output
BUSY
clear
245
246
Master device processing (transmitter) Program processing Hardware operation Transfer line
User's Manual U11302EJ4V0UM
Figure 13-28. Data Transmission from Master Device to Slave Device
Write to SIO0
Interrupt servicing (peparation for the next serial transfer)
Serial transmission
INTCSI0
generation
ACKD
set
SCK0
stop
CHAPTER 13
SCK0 pin
1
2
3
4
5
6
7
8
9
SERIAL INTERFACE CHANNEL 0
SB0 pin
D7
D6
D5
D4
D3 Data
D2
D1
D0
ACK
BUSY
READY
Slave device processing (receiver) Program processing
SIO0 read ACKT set
BUSY
clear
Hardware operation
Serial reception
INTCSI0
generation
ACK BUSY
output output
BUSY
clear
Figure 13-29. Data Transmission from Slave Device to Master Device
Master device processing (receiver) Program processing
FFH write to SIO0
SIO0 read
ACKT FFH write
set
to SIO0
Receive data processing
Hardware operation
SCK0
stop
Serial reception
INTCSI0
generation
ACK
output
Serial reception
CHAPTER 13
Transfer line
User's Manual U11302EJ4V0UM
SCK0 pin
1
2
3
4
5
6
7
8
9
1
2
SERIAL INTERFACE CHANNEL 0
BUSY SB0 pin
READY
D7
D6
D5
D4
D3 Data
D2
D1
D0
ACK
BUSY
READY
D7
D6
Slave device processing (transmitter) Program processing
Write to SIO0 Write to SIO0
Hardware operation
BUSY
clear
Serial transmission
INTCSI0
generation
ACKD
set
BUSY
output
BUSY
clear
247
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(9) Transfer start Serial transfer is started by setting transfer data to serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. * Serial interface channel 0 operation control bit (CSIE0) = 1 * Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer. Cautions 1. 2. If CSIE0 is set to "1" after data write to SIO0, transfer does not start. Because the N-ch open-drain output must be made to go into a high-impedance state during data reception, write FFH to SIO0 in advance. However, when the wakeup function specification bit (WUP) = 1, the N-ch open-drain output always goes into a high-impedance state. Thus, it is not necessary to write FFH to SIO0. 3. If data is written to SIO0 when the slave is busy, the data is not lost. When the busy state is cleared and SB0 (or SB1) input is set to the high level (READY) state, transfer starts. Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0) is set. For the pin that is to be used for data I/O (SB0 or SB1), be sure to set as follows before serial transfer of the 1st byte after RESET input. [1] Set the P25 and P26 output latches to 1. [2] Set bit 0 (RELT) of the serial bus interface control register (SBIC) to 1. [3] Reset the P25 and P26 output latches from 1 to 0. (10) Judging busy status of slave When the device is in the master mode, follow the procedure below to judge whether the slave device is in the busy state or not. [1] Detect acknowledge signal (ACK) or interrupt request signal generation. [2] Set the port mode register PM25 (or PM26) of the SB0/P25 (or SB1/P26) pin to the input mode. [3] Read out the pin state (when the pin level is high, the READY state is set). After detection of the READY state, set the port mode register to 0 and return to the output mode. (11) SBI mode precautions (a) Slave selection/non-selection is detected by match detection of the slave address received after bus release (RELD = 1). For this match detection, the match interrupt (CSIIF0) of the address to be generated with WUP = 1 is normally used. Thus, execute selection/non-selection detection by slave address when WUP = 1. (b) When detecting selection/non-selection without the use of an interrupt with WUP = 0, do so by means of transmission/reception of the command preset by program instead of using the address match detection method. (c) In SBI, after specifying reset of BUSY, the BUSY signal is output until the fall of the next serial clock (SCK0). If WUP = 1 is set during this interval by mistake, it will be impossible to reset BUSY. Therefore, after BUSY is released, make sure that the SB0 (SB1) pin is high level before setting WUP = 1.
248
User's Manual U11302EJ4V0UM
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(d) For the pin that is to be used for data I/O, be sure to set as follows before serial transfer of the 1st byte after RESET input. [1] Set the P25 and P26 output latches to 1. [2] Set bit 0 (RELT) of the serial bus interface control register (SBIC) to 1. [3] Reset the P25 and P26 output latches from 1 to 0. (e) If the SB0 (SB1) line changes from low level to high level or from high level to low level while the SCK0 line is high level, it is recognized as either a bus release signal or a command signal. Therefore, if the changing timing of the bus fluctuates because of substrate capacitance, etc., it may be recognized as a bus release signal (or a command signal) even while data is being transmitted. Care should therefore be taken in the wiring. 13.4.4 2-wire serial I/O mode operation The 2-wire serial I/O mode can handle any communication format by program. Communication is basically carried out using two lines: a serial clock (SCK0) and serial data input/output (SB0 or SB1). Figure 13-30. Serial Bus Configuration Example Using 2-Wire Serial I/O Mode
VDD VDD
Master
Slave
SCK0
SCK0
SB0 (SB1)
SB0 (SB1)
(1) Register setting The 2-wire serial I/O mode is set by serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specification register (SINT).
User's Manual U11302EJ4V0UM
249
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H.
Symbol <7> <6> <5> CSIM0 4 3 2 1 0 Address FF60H After reset 00H R/W R/WNote 1
CSIM CSIM CSIM CSIM CSIM CSIE0 COI WUP 04 03 02 01 00
R/W
CSIM CSIM 01 00 0 1 1 x 0 1
Serial interface channel 0 clock selection Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
R/W CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 04 03 02 0 1 x 0
Operating mode
Start bit
SI0/P25 pin function
SO0/P26 pin function
SCK0/P27 pin function
3-wire serial I/O mode (refer to 13.4.2 3-wire serial I/O mode operation) SBI mode (refer to 13.4.3 SBI mode operation) 2-wire serial I/O mode MSB P25 (CMOS I/O) SB1 SCK0 (N-ch open-drain (N-ch open-drain I/O) I/O) P26 (CMOS I/O)
Note 2 Note 2
0 1 1
x
x
0
0
0
1
Note 2 Note 2
1
0
0
x
x
0
1
SB0 (N-ch open-drain I/O)
R/W
WUP 0 1
Wakeup function control Note 3 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1) matches the slave address register (SVA) in SBI mode
R
COI 0 1
Slave address comparison result flag Note 4 Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data
R/W CSIE0 Serial interface channel 0 operation control 0 1 Operation stopped Operation enabled
Notes 1. 2. 3. 4.
Bit 6 (COI) is a read-only bit. Can be used freely as port function. Set WUP to 0 when the 2-wire serial I/O mode is selected. When CSIE0 = 0, COI becomes 0.
Remark x: don't care PMxx: Port mode register Pxx: Port output latch
250
User's Manual U11302EJ4V0UM
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SBIC to 00H.
Symbol
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
Address FF61H
After reset 00H
R/W R/W
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
R/W
RELT
When RELT = 1, the SO latch is set to 1. After SO latch setting, RELT is automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
R/W
CMDT
When CMDT = 1, the SO latch is cleared to 0. After SO latch clearance, CMDT is automatically cleared to 0. Also cleared to 0 when CSIE0 = 0.
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
User's Manual U11302EJ4V0UM
251
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(c) Interrupt timing specification register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SINT to 00H.
Symbol SINT 7 0 <6> CLD <5> <4> 3 0 2 0 1 0 0 0 Address FF63H After reset 00H R/W R/WNote 1
SIC SVAM
R/W SVAM 0 1 R/W SIC 0 1 INTCSI0 interrupt source selection CSIIF0 is set upon termination of serial interface channel 0 transfer CSIIF0 is set upon bus release detection or termination of serial interface channel 0 transfer SVA bit to be used as slave address Bits 0 to 7 Bits 1 to 7
R CLD 0 1
SCK0 pin levelNote 2 Low level High level
Notes 1. Bit 6 (CLD) is a read-only bit. 2. When CSIE0 = 0, CLD becomes 0. Caution Be sure to set bits 0 to 3 to 0. Remark SVA: Slave address register
CSIIF0: Interrupt request flag for INTCSI0 CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
252
User's Manual U11302EJ4V0UM
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/ reception is carried out bit by bit in synchronization with the serial clock. Shift operations of serial I/O shift register 0 (SIO0) are carried out in synchronization with the falling edge of the serial clock (SCK0). The transmit data is held in the SO0 latch and is output from the SB0/P25 (or SB1/P26) pin with the MSB set as the start bit. The receive data input from the SB0 (or SB1) pin is latched into SIO0 at the rising edge of SCK0. Upon termination of 8-bit transfer, SIO0 operation stops automatically and the interrupt request flag (CSIIF0) is set. Figure 13-31. 2-Wire Serial I/O Mode Timing
SCK0
1
2
3
4
5
6
7
8
SB0/SB1
D7
D6
D5
D4
D3
D2
D1
D0
CSIIF0 End of transfer Transfer start at the falling edge of SCK0
The SB0 (SB1) pin specified for the serial data bus is an N-ch open-drain I/O and thus it must be externally pulled up. Because the N-ch open-drain output must be high impedance for data reception, write FFH to SIO0 in advance. The SB0 (or SB1) pin generates the SO0 latch status and thus the SB0 (or SB1) pin output status can be manipulated by setting bit 0 (RELT) and bit 1 (CMDT) of the serial bus interface control register (SBIC). However, do not carry out this manipulation during serial transfer. Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27 output latch (refer to 13.4.5 SCK0/P27 pin output manipulation).
User's Manual U11302EJ4V0UM
253
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
(3) Signals Figure 13-32 shows the RELT and CMDT operations. Figure 13-32. RELT and CMDT Operations
SO0 latch
RELT
CMDT
(4) Transfer start Serial transfer is started by setting transfer data to serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. * Serial interface channel 0 operation control bit (CSIE0) = 1 * Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer. Cautions 1. If CSIE0 is set to "1" after data write to SIO0, transfer does not start. 2. Because the N-ch open-drain output must be high impedance for data reception, write FFH to SIO0 in advance. Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0) is set. (5) Error detection In the 2-wire serial I/O mode, the serial bus SB0 (SB1) status being transmitted is fetched into serial I/ O shift register 0 (SIO0) of the transmitting device. Thus, transmit errors can be detected in the following two ways. (a) Comparison of SIO0 data before transmission to that after transmission In this case, if the two data differ, a transmit error is judged to have occurred. (b) Use of the slave address register (SVA) Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, the COI bit (match signal coming from the address comparator) of serial operating mode register 0 (CSIM0) is tested. If "1", normal transmission is judged to have been carried out. If "0", a transmit error is judged to have occurred.
254
User's Manual U11302EJ4V0UM
CHAPTER 13
SERIAL INTERFACE CHANNEL 0
13.4.5 SCK0/P27 pin output manipulation Because the SCK0/P27 pin incorporates an output latch, static output is also possible by software in addition to normal serial clock output. P27 output latch manipulation enables any value of SCK0 to be set by software (SI0/SB0 and SO0/SB1 pins to be controlled with bit 0 (RELT) and bit 1 (CMDT) of the serial bus interface control register (SBIC)). The SCK0/P27 pin output manipulation procedure is described below. [1] Set serial operating mode register 0 (CSIM0) (SCK0 pin enabled for serial operation in the output mode). SCK0 = 1 with serial transfer suspended. [2] Manipulate the P27 output latch with a bit manipulation instruction. Figure 13-33. SCK0/P27 Pin Configuration
Set with a bit manipulation instruction SCK0/P27 To internal circuit P27 output latch
When CSIE0 = 1 and CSIM01 and CSIM00 = 1, 0 or 1, 1, respectively
SCK0 (set to 1 while transfer is stopped) From serial clock controller
User's Manual U11302EJ4V0UM
255
CHAPTER 14 SERIAL INTERFACE CHANNEL 1
14.1 Functions of Serial Interface Channel 1
Serial interface channel 1 has the following three modes. Table 14-1. Modes of Serial Interface Channel 1
Operation Mode Operation stop mode 3-wire serial I/O mode (MSB-/LSB-first switchable) Pins Used - Features * Used when serial transfer is not carried out. * Power consumption can be reduced. * Input and output lines are independent and they can transfer/receive at the same time, so the data transfer processing time is short. * The start bit of 8-bit data to undergo serial transfer is switchable between MSB and LSB. * Mode with same function as 3-wire serial I/O mode above plus automatic transmit/receive function. * Can transmit/receive data with a maximum of 64 bytes. Therefore, this function enables the hardware to transmit/receive data to/from the OSD (On Screen Display) device and device with on-chip display controller/driver independently of the CPU thus the software load can be reduced. Usage -
SCK1 (serial clock), SO1 (serial output), SI1 (serial input)
These modes are used for connection of peripheral ICs and display controllers that incorporate a clocked serial interface.
3-wire serial I/O SCK1 (serial clock), mode with SO1 (serial output), automatic transmit/ SI1 (serial input) receive function (MSB-/LSB-first switchable)
256
User's Manual U11302EJ4V0UM
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
14.2 Configuration of Serial Interface Channel 1
Serial interface channel 1 consists of the following hardware. Table 14-2. Configuration of Serial Interface Channel 1
Item Registers Configuration Serial I/O shift register 1 (SIO1) Automatic data transmit/receive address pointer (ADTP) Timer clock select register 3 (TCL3) Serial operating mode register 1 (CSIM1) Automatic data transmit/receive control register (ADTC) Automatic data transmit/receive interval specification register (ADTI) Port mode register 2 (PM2) Note
Control registers
Note Refer to Figure 4-5 Block Diagram of P20, P21, P23 to P26 and Figure 4-6 Block Diagram of P22 and P27.
User's Manual U11302EJ4V0UM
257
Selector
258
Internal bus Buffer RAM ATE DIR Serial I/O shift register 1 (SIO1) DIR SI1/P20 PM21 SO1/P21 PM23 STB/P23 BUSY/P24 Handshake P21 output latch
User's Manual U11302EJ4V0UM
Figure 14-1. Block Diagram of Serial Interface Channel 1
Automatic data transmit/receive address pointer (ADTP)
Internal bus
Automatic data transmit/ receive interval specification register
Automatic data transmit/ receive control register
TRF STRB BUSY BUSY 1 0
Serial operating mode register 1 CSIE1 DIR ATE CSIM CSIM
11 10
CHAPTER 14
ADTI ADTI ADTI ADTI ADTI ADTI 7 4 3 2 1 0 Match ADTI0 to ADTI4
RE
ARLD ERCE ERR
SERIAL INTERFACE CHANNEL 1
5-bit counter
ARLD Serial clock counter
SIO1 write
INTCSI1
Clear
SCK1/P22
R Q S P22 output latch
Selector TO2
Selector
4
fx/22 to fx/29
PM22
TCL TCL TCL TCL 37 36 35 34
Timer clock select register 3
Internal bus
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
(1) Serial I/O shift register 1 (SIO1) This is an 8-bit register used to carry out parallel/serial conversion and serial transmission/reception (shift operations) in synchronization with the serial clock. SIO1 is set with an 8-bit memory manipulation instruction. When bit 7 (CSIE1) of serial operating mode register 1 (CSIM1) is 1, writing data to SIO1 starts serial operation. In transmission, data written to SIO1 is output to the serial output (SO1). In reception, data is read from the serial input (SI1) to SIO1. RESET input makes SIO1 undefined. Caution Do not write data to SIO1 while the automatic transmit/receive function is activated. (2) Automatic data transmit/receive address pointer (ADTP) This register stores the value of (the number of transmit data bytes - 1) while the automatic transmit/ receive function is activated. It is decremented automatically with data transmission/reception. ADTP is set with an 8-bit memory manipulation instruction. The higher 3 bits must be set to 0. RESET input sets ADTP to 00H. Caution Do not write data to ADTP while the automatic transmit/receive function is activated. (3) Serial clock counter This counter counts the serial clocks to be output and input during transmission/reception and checks whether 8-bit data has been transmitted/received.
User's Manual U11302EJ4V0UM
259
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
14.3 Control Registers of Serial Interface Channel 1
The following four registers are used to control serial interface channel 1. * Timer clock select register 3 (TCL3) * Serial operating mode register 1 (CSIM1) * Automatic data transmit/receive control register (ADTC) * Automatic data transmit/receive interval specification register (ADTI)
260
User's Manual U11302EJ4V0UM
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
(1) Timer clock select register 3 (TCL3) This register sets the serial clock of serial interface channel 1. TCL3 is set with an 8-bit memory manipulation instruction. RESET input sets TCL3 to 88H. Remark Besides setting the serial clock of serial interface channel 1, TCL3 sets the serial clock of serial interface channel 0. Figure 14-2. Format of Timer Clock Select Register 3
Symbol 7 6 5 4 3 2 1 0 Address FF43H After reset 88H R/W R/W
TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30
Serial interface channel 0 TCL33 TCL32 TCL31 TCL30 serial clock selection 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 fX/2 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/26 (78.1 kHz) fX/27 (39.1 kHz) fX/28 (19.5 kHz) fX/29 (9.8 kHz) Setting prohibited
2
Other than above
Serial interface channel 1 TCL37 TCL36 TCL35 TCL34 serial clock selection 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 fX/22 (1.25 MHz) fX/23 (625 kHz) fX/24 (313 kHz) fX/25 (156 kHz) fX/2 (78.1 kHz) fX/27 (39.1 kHz)
8 fX/2 (19.5 kHz) 6
fX/29 (9.8 kHz) Setting prohibited
Other than above
Caution
If TCL3 is to be rewritten with data that is not identical, stop the serial transfer first.
Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 5.0 MHz.
User's Manual U11302EJ4V0UM
261
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
(2) Serial operating mode register 1 (CSIM1) This register sets the serial interface channel 1 serial clock, operating mode, operation enable/stop, and automatic transmit/receive operation enable/stop. CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM1 to 00H. Figure 14-3. Format of Serial Operating Mode Register 1
Symbol <7> CSIM1 6 <5>
ATE
4
0
3
0
2
0
1
0
Address FF68H
After reset 00H
R/W R/W
CSIE1 DIR
CSIM CSIM 11 10
CSIM CSIM 11 10 0 1 1 x 0 1
Serial interface channel 1 clock selection Clock externally input to SCK1 pin Note 1 8-bit timer register 2 (TM2) output Clock specified with bits 4 to 7 of timer clock select register 3 (TCL3)
ATE 0 1
Serial interface channel 1 operating mode selection 3-wire serial I/O mode 3-wire serial I/O mode with automatic transmit/receive function
DIR 0 1 MSB LSB
Start bit
SI1 pin function SI1/P20 (input)
SO1 pin function SO1 (CMOS output)
CSIE1
CSIM 11
PM20 P20 PM21 P21 PM22 P22
Shift register 1 operation Operation stop
Serial clock counter operation control Clear
SI1/P20 pin function P20 (CMOS I/O)
SO1/P21 pin function P21 (CMOS I/O)
SCK1/P22 pin function P22 (CMOS I/O)
Note 2 Note 2 Note 2 Note 2 Note 2 Note 2
0
x
x
x
x
x
x
x
0
Note 3 Note 3
1 1 x 0 0 0
x
Operation enable Count operation
SI1Note 3 (input)
SO1 (CMOS output)
SCK1 (input) SCK1 (CMOS output)
1 1
1
Notes 1. If external clock input has been selected with CSIM11 set to 0, set bit 1 (BUSY1) and bit 2 (STRB) of the automatic data transmit/receive control register (ADTC) to 0, 0. 2. Can be used freely as a port pin. 3. Can be used as P20 when used only for transmission (set bit 7 (RE) of ADTC to 0). Remark x: Pxx: don't care Port output latch
PMxx: Port mode register
262
User's Manual U11302EJ4V0UM
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
(3) Automatic data transmit/receive control register (ADTC) This register sets automatic receive enable/disable, the operating mode, strobe output enable/disable, busy input enable/disable, error check enable/disable, and displays automatic transmit/receive execution and error detection. ADTC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTC to 00H.
User's Manual U11302EJ4V0UM
263
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
Figure 14-4. Format of Automatic Data Transmit/Receive Control Register
Symbol ADTC
<7> RE
<6>
<5>
<4>
<3>
<2>
<1>
<0>
Address FF69H
After reset 00H
R/W R/WNote 1
ARLD ERCE ERR
TRF STRB BUSY1 BUSY0
R/W
BUSY1 BUSY0 0 1 1 x 0 1
Busy input control Not using busy input Busy input enabled (active high) Busy input enabled (active low)
R/W
STRB 0 1
Strobe output control Strobe output disabled Strobe output enabled Status of automatic transmit/receive functionNote 2 Detection of termination of automatic transmission/ reception (This bit is set to 0 upon suspension of automatic transmission/reception or when ARLD = 0.) During automatic transmission/reception (This bit is set to 1 when data is written to SIO1.) Error detection of automatic transmit/receive function No error (This bit is set to 0 when data is written to SIO1.) Error occurred Error check control of automatic transmit/ receive function Error check disabled Error check enabled (only when BUSY1 = 1) Operating mode selection of automatic transmit/ receive function Single operating mode Repetitive operating mode Receive control of automatic transmit/receive function Receive disabled Receive enabled
R
TRF 0
1 R
ERR
0 1 R/W ERCE 0 1 R/W ARLD 0 1 R/W RE 0 1
Notes 1. Bits 3 and 4 (TRF and ERR) are read-only bits. 2. The termination of automatic transmission/reception should be judged by using TRF, not CSIIF1 (interrupt request flag). Caution When external clock input is selected with bit 1 (CSIM11) of serial operating mode register 1 (CSIM1) set to 0, set STRB and BUSY1 of ADTC to 0, 0. Remark x: don't care
264
User's Manual U11302EJ4V0UM
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
(4) Automatic data transmit/receive interval specification register (ADTI) This register sets the automatic transmit/receive function data transfer interval. ADTI is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTI to 00H. Figure 14-5. Format of Automatic Data Transmit/Receive Interval Specification Register (1/2)
Symbol 7 6 0 5 0 4 3 2 1 0 Address FF6BH After reset 00H R/W R/W
ADTI ADTI7
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
ADTI7 0 1
Data transfer interval control No control of interval by ADTI Note 1 Control of interval by ADTI (ADTI0 to ADTI4)
Data transfer interval specification (fX = 5.0 MHz operation) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Minimum Note 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 36.8 s + 0.5/fSCK 62.4 s + 0.5/fSCK 88.0 s + 0.5/fSCK 113.6 s + 0.5/fSCK 139.2 s + 0.5/fSCK 164.8 s + 0.5/fSCK 190.4 s + 0.5/fSCK 216.0 s + 0.5/fSCK 241.6 s + 0.5/fSCK 267.2 s + 0.5/fSCK 292.8 s + 0.5/fSCK 318.4 s + 0.5/fSCK 344.0 s + 0.5/fSCK 369.6 s + 0.5/fSCK 395.2 s + 0.5/fSCK 420.8 s + 0.5/fSCK Maximum Note 2 40.0 s + 1.5/fSCK 65.6 s + 1.5/fSCK 91.2 s + 1.5/fSCK 116.8 s + 1.5/fSCK 142.4 s + 1.5/fSCK 168.0 s + 1.5/fSCK 193.6 s + 1.5/fSCK 219.2 s + 1.5/fSCK 244.8 s + 1.5/fSCK 270.4 s + 1.5/fSCK 296.0 s + 1.5/fSCK 321.6 s + 1.5/fSCK 347.2 s + 1.5/fSCK 372.8 s + 1.5/fSCK 398.4 s + 1.5/fSCK 424.0 s + 1.5/fSCK
User's Manual U11302EJ4V0UM
265
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
Notes 1. The interval is dependent only on CPU processing. 2. The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if the minimum calculated by the following expression is smaller than 2/fSCK, the minimum interval time is 2/fSCK. Minimum = (n + 1) x Maximum = (n + 1) x 27 fX 27 fX + + 56 fX 72 fX + + 0.5 fSCK 1.5 fSCK
Cautions 1. ADTI should not be written to during operation of the automatic transmit/receive function. 2. Bits 5 and 6 must be set to 0. 3. When ADTI is used to control the interval time of data transfer by automatic transmit/ receive function, busy control (refer to 14.4.3 (4) (a) Busy control option) is invalid. Remarks 1. fX: Main system clock oscillation frequency
2. fSCK: Serial clock frequency
266
User's Manual U11302EJ4V0UM
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
Figure 14-5. Format of Automatic Data Transmit/Receive Interval Specification Register (2/2)
Symbol 7 6 0 5 0 4 3 2 1 0 Address FF6BH After reset 00H R/W R/W
ADTI ADTI7
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
Data transfer interval specification (fX = 5.0 MHz operation) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Minimum Note 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 446.4 s + 0.5/fSCK 472.0 s + 0.5/fSCK 497.6 s + 0.5/fSCK 523.2 s + 0.5/fSCK 548.8 s + 0.5/fSCK 574.4 s + 0.5/fSCK 600.0 s + 0.5/fSCK 625.6 s + 0.5/fSCK 651.2 s + 0.5/fSCK 676.8 s + 0.5/fSCK 702.4 s + 0.5/fSCK 728.0 s + 0.5/fSCK 753.6 s + 0.5/fSCK 779.2 s + 0.5/fSCK 804.8 s + 0.5/fSCK 830.4 s + 0.5/fSCK Maximum Note 449.6 s + 1.5/fSCK 475.2 s + 1.5/fSCK 500.8 s + 1.5/fSCK 526.4 s + 1.5/fSCK 552.0 s + 1.5/fSCK 577.6 s + 1.5/fSCK 603.2 s + 1.5/fSCK 628.8 s + 1.5/fSCK 654.4 s + 1.5/fSCK 680.0 s + 1.5/fSCK 705.6 s + 1.5/fSCK 731.2 s + 1.5/fSCK 756.8 s + 1.5/fSCK 782.4 s + 1.5/fSCK 808.0 s + 1.5/fSCK 833.6 s + 1.5/fSCK
Note
The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if the minimum calculated by the following expression is smaller than 2/fSCK, the minimum interval time is 2/fSCK. Minimum = (n + 1) x 27 fX 27 fX + 56 fX 72 fX + 0.5 fSCK 1.5 fSCK
Maximum = (n + 1) x
+
+
Cautions 1. ADTI should not be written to during operation of the automatic transmit/receive function. 2. Bits 5 and 6 must be set to 0. 3. When ADTI is used to control the interval time of data transfer by automatic transmit/ receive function, busy control (refer to 14.4.3 (4) (a) Busy control option) is invalid. Remarks 1. fX: Main system clock oscillation frequency
2. fSCK: Serial clock frequency
User's Manual U11302EJ4V0UM
267
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
14.4 Operations of Serial Interface Channel 1
The following three operating modes are available for serial interface channel 1. * Operation stop mode * 3-wire serial I/O mode * 3-wire serial I/O mode with automatic transmit/receive function 14.4.1 Operation stop mode Serial transfer is not carried out in the operation stop mode. Thus, power consumption can be reduced. Serial I/O shift register 1 (SIO1) does not carry out shift operations and can be used as an ordinary 8-bit register. In the operation stop mode, the P20/SI1, P21/SO1, P22/SCK1, P23/STB, and P24/BUSY pins can be used as ordinary I/O ports. (1) Register setting The operation stop mode is set by serial operating mode register 1 (CSIM1). CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM1 to 00H.
Symbol <7> CSIM1
6
<5>
ATE
4
0
3
0
2
0
1
0
Address FF68H
After reset 00H
R/W R/W
CSIE1 DIR
CSIM CSIM 10 11
CSIE1
CSIM 11
PM20 P20 PM21 P21 PM22 P22
Shift register 1 operation Operation stop
Serial clock counter operation control Clear
SI1/P20 pin function P20 (CMOS I/O)
SO1/P21 pin function P21 (CMOS I/O)
SCK1/P22 pin function P22 (CMOS I/O)
Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
0
x
x
x
x
x
x
x
0
Note 2 Note 2
1 1 x 0 0 0
x
Operation enable Count operation
SI1Note 2 (input)
SO1 (CMOS output)
SCK1 (input) SCK1 (CMOS output)
1 1
1
Notes 1. Can be used freely as a port pin. 2. Can be used as P20 (CMOS I/O) when used only for transmission (set bit 7 (RE) of the automatic data transmit/receive control register (ADTC) to 0). Remark x: Pxx: don't care Port output latch
PMxx: Port mode register
268
User's Manual U11302EJ4V0UM
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
14.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is used for connection of peripheral ICs and display controllers that incorporate a clocked serial interface. Communication is carried out using three lines: a serial clock (SCK1), serial output (SO1), and serial input (SI1). (1) Register setting The 3-wire serial I/O mode is set by serial operating mode register 1 (CSIM1). CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM1 to 00H.
Symbol <7> CSIM1 6 <5>
ATE
4
0
3
0
2
0
1
0
Address FF68H
After reset 00H
R/W R/W
CSIE1 DIR
CSIM CSIM 10 11
CSIM CSIM 11 10 0 1 1 x 0 1
Serial interface channel 1 clock selection Clock externally input to SCK1 pin Note 1 8-bit timer register 2 (TM2) output Clock specified with bits 4 to 7 of timer clock select register 3 (TCL3)
ATE 0 1
Serial interface channel 1 operating mode selection 3-wire serial I/O mode 3-wire serial I/O mode with automatic transmit/receive function
DIR 0 1 MSB LSB
Start bit
SI1 pin function SI1/P20 (input)
SO1 pin function SO1 (CMOS output)
CSIE1
CSIM 11
PM20 P20 PM21 P21 PM22 P22
Shift register 1 operation Operation stop
Serial clock counter operation control Clear
SI1/P20 pin function P20 (CMOS I/O)
SO1/P21 pin function P21 (CMOS I/O)
SCK1/P22 pin function P22 (CMOS I/O)
Note 2 Note 2 Note 2 Note 2 Note 2 Note 2
0
x
x
x
x
x
x
x
0
Note 3 Note 3
1 1 x 0 0 0
x
Operation enable Count operation
SI1Note 3 (input)
SO1 (CMOS output)
SCK1 (input) SCK1 (CMOS output)
1 1
1
Notes 1. If external clock input has been selected with CSIM11 set to 0, set bit 1 (BUSY1) and bit 2 (STRB) of the automatic data transmit/receive control register (ADTC) to 0, 0. 2. Can be used freely as a port pin. 3. Can be used as P20 when used only for transmission (set bit 7 (RE) of ADTC to 0). Remark x: don't care PMxx: Port mode register Pxx: Port output latch
User's Manual U11302EJ4V0UM
269
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
(2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/ reception is carried out bit by bit in synchronization with the serial clock. Shift operations of serial I/O shift register 1 (SIO1) are carried out at the falling edge of the serial clock (SCK1). The transmit data is held in the SO1 latch and is output from the SO1 pin. The receive data input to the SI1 pin is latched into SIO1 at the rising edge of SCK1. Upon termination of 8-bit transfer, the SIO1 operation stops automatically and the interrupt request flag (CSIIF1) is set. Figure 14-6. 3-Wire Serial I/O Mode Timing
SCK1
1
2
3
4
5
6
7
8
SI1
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO1
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
CSIIF1 End of transfer Transfer start at the falling edge of SCK1 SIO1 write
Caution
The SO1 pin becomes low level by SIO1 write.
270
User's Manual U11302EJ4V0UM
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
(3) MSB/LSB switching as the start bit In the 3-wire serial I/O mode, transfer can be selected to start from the MSB or LSB. Figure 14-7 shows the configuration of serial I/O shift register 1 (SIO1) and the internal bus. As shown in the figure, the MSB/LSB can be read/written in reverse form. MSB/LSB switching as the start bit can be specified using bit 6 (DIR) of serial operating mode register 1 (CSIM1). Figure 14-7. Circuit for Switching Transfer Bit Order
7 6 Internal bus 1 0 LSB-first MSB-first Read/write gate Read/write gate
SO1 latch SI1 Shift register 1 (SIO1) D Q
SO1
SCK1
Start bit switching is realized by switching the bit order for data write to SIO1. The SIO1 shift order remains unchanged. Thus, switching between MSB-first and LSB-first must be performed before writing data to the shift register. (4) Transfer start Serial transfer is started by setting transfer data to serial I/O shift register 1 (SIO1) when the following two conditions are satisfied. * Serial interface channel 1 operation control bit (CSIE1) = 1 * Internal serial clock is stopped or SCK1 is at high level after 8-bit serial transfer. Caution If CSIE1 is set to "1" after data write to SIO1, transfer does not start.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF1) is set.
User's Manual U11302EJ4V0UM
271
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
14.4.3
3-wire serial I/O mode operation with automatic transmit/receive function
This 3-wire serial I/O mode is used for transmission/reception of up to 64-byte data without using software. Once transfer is started, the set number of bytes of the data prestored in the RAM can be transmitted, and the set number of bytes of data can be received and stored in the RAM. Handshake signals (STB and BUSY) are supported by hardware to transmit/receive data continuously. An OSD (On Screen Display) LSI and peripheral LSI including an LCD controller/driver can be connected without difficulty. (1) Register setting The 3-wire serial I/O mode with automatic transmit/receive function is set by serial operating mode register 1 (CSIM1), the automatic data transmit/receive control register (ADTC), and the automatic data transmit/receive interval specification register (ADTI).
272
User's Manual U11302EJ4V0UM
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
(a) Serial operating mode register 1 (CSIM1) CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM1 to 00H.
Symbol <7> CSIM1 6 <5>
ATE
4
0
3
0
2
0
1
0
Address FF68H
After reset 00H
R/W R/W
CSIE1 DIR
CSIM CSIM 10 11
CSIM CSIM 11 10 0 1 1 x 0 1
Serial interface channel 1 clock selection Clock externally input to SCK1 pin Note 1 8-bit timer register 2 (TM2) output Clock specified with bits 4 to 7 of timer clock select register 3 (TCL3)
ATE 0 1
Serial interface channel 1 operating mode selection 3-wire serial I/O mode 3-wire serial I/O mode with automatic transmit/receive function
DIR 0 1 MSB LSB
Start bit
SI1 pin function SI1/P20 (input)
SO1 pin function SO1 (CMOS output)
CSIE1
CSIM 11
PM20 P20 PM21 P21 PM22 P22
Shift register 1 operation Operation stop
Serial clock counter operation control Clear
SI1/P20 pin function P20 (CMOS I/O)
SO1/P21 pin function P21 (CMOS I/O)
SCK1/P22 pin function P22 (CMOS I/O)
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
0
x
x
x
x
x
x
x
0
Note 3 Note 3
1 1 x 0 0 0
x
Operation enable Count operation
SI1 Note 3 (input)
SO1 (CMOS output)
SCK1 (input) SCK1 (CMOS output)
1 1
1
Notes 1. If external clock input has been selected with CSIM11 set to 0, set bit 1 (BUSY1) and bit 2 (STRB) of the automatic data transmit/receive control register (ADTC) to 0, 0. 2. Can be used freely as a port pin. 3. Can be used as P20 when used only for transmission (set bit 7 (RE) of ADTC to 0). Remark x: don't care PMxx: Port mode register Pxx: Port output latch
User's Manual U11302EJ4V0UM
273
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
(b) Automatic data transmit/receive control register (ADTC) ADTC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTC to 00H.
Symbol ADTC <7> RE <6> <5> <4> <3> <2> <1> <0> Address FF69H After reset 00H R/W R/WNote 1
ARLD ERCE ERR
TRF STRB BUSY1 BUSY0
R/W
BUSY1 BUSY0 Busy input control 0 1 1 x 0 1 Not using busy input Busy input enabled (active high) Busy input enabled (active low)
R/W
STRB 0 1
Strobe output control Strobe output disabled Strobe output enabled
R
TRF 0
Status of automatic transmit/receive functionNote 2 Detection of termination of automatic transmission/ reception (This bit is set to 0 upon suspension of automatic transmission/reception or when ARLD = 0.) During automatic transmission/reception (This bit is set to 1 when data is written to SIO1.)
1 R
ERR 0 1
Error detection of automatic transmit/receive function No error (This bit is set to 0 when data is written to SIO1.) Error occurred
R/W
ERCE 0 1
Error check control of automatic transmit/ receive function Error check disabled Error check enabled (only when BUSY1 = 1)
R/W
ARLD 0 1
Operating mode selection of automatic transmit/ receive function Single operating mode Repetitive operating mode
R/W
RE 0 1
Receive control of automatic transmit/receive function Receive disabled Receive enabled
Notes 1. Bits 3 and 4 (TRF and ERR) are read-only bits. 2. The termination of automatic transmission/reception should be judged by using TRF, not CSIIF1 (interrupt request flag). Caution When external clock input is selected with bit 1 (CSIM11) of serial operating mode register 1 (CSIM1) set to 0, set STRB and BUSY1 of ADTC to 0, 0 (handshake control cannot be executed when an external clock is input). Remark x: don't care
274
User's Manual U11302EJ4V0UM
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
(c) Automatic data transmit/receive interval specification register (ADTI) This register sets the data transfer interval of the automatic transmit/receive function. ADTI is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ADTI to 00H.
Symbol 7 6 0 5 0 4 3 2 1 0 Address FF6BH After reset 00H R/W R/W
ADTI ADTI7
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
ADTI7 0 1
Data transfer interval control No control of interval by ADTI Note 1 Control of interval by ADTI (ADTI0 to ADTI4)
Data transfer interval specification (fX = 5.0 MHz operation) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Minimum Note 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 36.8 s + 0.5/fSCK 62.4 s + 0.5/fSCK 88.0 s + 0.5/fSCK 113.6 s + 0.5/fSCK 139.2 s + 0.5/fSCK 164.8 s + 0.5/fSCK 190.4 s + 0.5/fSCK 216.0 s + 0.5/fSCK 241.6 s + 0.5/fSCK 267.2 s + 0.5/fSCK 292.8 s + 0.5/fSCK 318.4 s + 0.5/fSCK 344.0 s + 0.5/fSCK 369.6 s + 0.5/fSCK 395.2 s + 0.5/fSCK 420.8 s + 0.5/fSCK Maximum Note 2 40.0 s + 1.5/fSCK 65.6 s + 1.5/fSCK 91.2 s + 1.5/fSCK 116.8 s + 1.5/fSCK 142.4 s + 1.5/fSCK 168.0 s + 1.5/fSCK 193.6 s + 1.5/fSCK 219.2 s + 1.5/fSCK 244.8 s + 1.5/fSCK 270.4 s + 1.5/fSCK 296.0 s + 1.5/fSCK 321.6 s + 1.5/fSCK 347.2 s + 1.5/fSCK 372.8 s + 1.5/fSCK 398.4 s + 1.5/fSCK 424.0 s + 1.5/fSCK
User's Manual U11302EJ4V0UM
275
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
Notes 1. The interval is dependent only on CPU processing. 2. The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: minimum interval time is 2/fSCK. Minimum = (n + 1) x 27 fX 27 fX + 56 fX 72 fX + 0.5 fSCK 1.5 fSCK Value set in ADTI0 to ADTI4). However, if the minimum calculated by the following expression is smaller than 2/fSCK, the
Maximum = (n + 1) x
+
+
Cautions 1. ADTI should not be written to during operation of the automatic transmit/receive function. 2. Bits 5 and 6 must be set to 0. 3. When ADTI is used to control the interval time of data transfer by automatic transmit/receive function, busy control (refer to 14.4.3 (4) (a) Busy control option) is invalid. Remarks 1. fX: Main system clock oscillation frequency
2. fSCK: Serial clock frequency
276
User's Manual U11302EJ4V0UM
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
Symbol
7
6 0
5 0
4
3
2
1
0
Address FF6BH
After reset 00H
R/W R/W
ADTI ADTI7
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
Data transfer interval specification (fX = 5.0 MHz operation) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Minimum Note 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 446.4 s + 0.5/fSCK 472.0 s + 0.5/fSCK 497.6 s + 0.5/fSCK 523.2 s + 0.5/fSCK 548.8 s + 0.5/fSCK 574.4 s + 0.5/fSCK 600.0 s + 0.5/fSCK 625.6 s + 0.5/fSCK 651.2 s + 0.5/fSCK 676.8 s + 0.5/fSCK 702.4 s + 0.5/fSCK 728.0 s + 0.5/fSCK 753.6 s + 0.5/fSCK 779.2 s + 0.5/fSCK 804.8 s + 0.5/fSCK 830.4 s + 0.5/fSCK MaximumNote 449.6 s + 1.5/fSCK 475.2 s + 1.5/fSCK 500.8 s + 1.5/fSCK 526.4 s + 1.5/fSCK 552.0 s + 1.5/fSCK 577.6 s + 1.5/fSCK 603.2 s + 1.5/fSCK 628.8 s + 1.5/fSCK 654.4 s + 1.5/fSCK 680.0 s + 1.5/fSCK 705.6 s + 1.5/fSCK 731.2 s + 1.5/fSCK 756.8 s + 1.5/fSCK 782.4 s + 1.5/fSCK 808.0 s + 1.5/fSCK 833.6 s + 1.5/fSCK
Note
The data transfer interval includes an error. The data transfer minimum and maximum intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if the minimum calculated by the following expression is smaller than 2/fSCK, the minimum interval time is 2/fSCK. Minimum = (n + 1) x 27 fX 27 fX + 56 fX 72 fX + 0.5 fSCK 1.5 fSCK
Maximum = (n + 1) x
+
+
Cautions 1. ADTI should not be written to during operation of the automatic transmit/receive function. 2. Bits 5 and 6 must be set to 0. 3. When ADTI is used to control the interval time of data transfer by automatic transmit/ receive function, busy control (refer to 14.4.3 (4) (a) Busy control option) is invalid. Remarks 1. fX: Main system clock oscillation frequency
2. fSCK: Serial clock frequency
User's Manual U11302EJ4V0UM
277
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
(2) Automatic transmit/receive data setting (a) Transmit data setting [1] Write transmit data from the least significant address of buffer RAM, FAC0H (up to FAFFH). The transmit data should be in the order from higher address to lower address. [2] Set the automatic data transmit/receive address pointer (ADTP) to the value obtained by subtracting 1 from the number of transmit data bytes. (b) Automatic transmit/receive mode setting [1] Set bit 7 (CSIE1) and bit 5 (ATE) of serial operating mode register 1 (CSIM1) to 1. [2] Set RE of the automatic data transmit/receive control register (ADTC) to 1. [3] Set the data transmit/receive transfer interval in the automatic data transmit/receive interval specification register (ADTI). [4] Write any value to serial I/O shift register 1 (SIO1) (transfer start trigger). Caution Writing any value to SIO1 orders the start of an automatic transmit/receive operation; the written value has no meaning. The following operations are automatically carried out when (a) and (b) are carried out. * After the buffer RAM data specified by ADTP is transferred to SIO1, transmission is carried out (start of automatic transmission/reception). * The received data is written to the buffer RAM address specified by ADTP. * ADTP is decremented and the next data transmission/reception is carried out. data of address FAC0H is output (end of automatic transmission/reception). * When automatic transmission/reception is terminated, bit 3 (TRF) of ADTC is cleared to 0. Data transmission/reception continues until the ADTP decremental output becomes 00H and the
278
User's Manual U11302EJ4V0UM
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
(3) Communication operation (a) Basic transmission/reception mode This transmission/reception mode is the same as the 3-wire serial I/O mode in which the specified number of data are transmitted/received in 8-bit units. Serial transfer is started when any data is written to serial I/O shift register 1 (SIO1) while bit 7 (CSIE1) of serial operating mode register 1 (CSIM1) is set to 1. Upon completion of transmission of the last byte, the interrupt request flag (CSIIF1) is set. However, the termination of automatic transmission/reception should be judged by bit 3 (TRF) of the automatic data transmit/receive control register (ADTC), not CSIIF1. If busy control and strobe control are not executed, the P23/STB and P24/BUSY pins can be used as normal I/O ports. Figure 14-8 shows the basic transmission/reception mode operation timing, and Figure 14-9 shows the operation flowchart. The operation of the buffer RAM to transmit/receive 6-byte data is shown in Figure 14-10. Figure 14-8. Basic Transmission/Reception Mode Operation Timing
Interval SCK1 SO1 SI1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
CSIIF1 TRF
Cautions 1. Because, in the basic transmission/reception mode, the automatic transmit/ receive function writes/reads data to/from the buffer RAM after 1-byte transmission/ reception, an interval is inserted until the next transmission/reception. As the buffer RAM write/read is performed at the same time as CPU processing, the maximum interval is dependent upon CPU processing and the value of the automatic data transmit/receive interval specification register (ADTI) (see (5) Automatic transmit/receive interval). 2. When TRF is cleared, the SO1 pin becomes low level. Remark CSIIF1: Interrupt request flag TRF: Bit 3 of the automatic data transmit/receive control register (ADTC)
User's Manual U11302EJ4V0UM
279
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
Figure 14-9. Basic Transmission/Reception Mode Flowchart
Start
Write transmit data in buffer RAM
Set ADTP to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes
Software execution
Set the transmission/reception operation interval time in ADTI
Write any data to SIO1 (Start trigger)
Write transmit data from buffer RAM to SIO1
Transmission/reception operation
Decrement pointer value
Hardware execution Write receive data from SIO1 to buffer RAM
Pointer value = 0
No
Yes
TRF = 0
No Software execution
Yes End
ADTP: Automatic data transmit/receive address pointer ADTI: Automatic data transmit/receive interval specification register SIO1: Serial I/O shift register 1 TRF: Bit 3 of the automatic data transmit/receive control register (ADTC)
280
User's Manual U11302EJ4V0UM
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
In 6-byte transmission/reception (ARLD = 0, RE = 1) in basic transmission/reception mode, buffer RAM operates as follows. (i) Before transmission/reception (refer to Figure 14-10 (a)) After arbitrary data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1. When transmission of the first byte is completed, receive data 1 (R1) is transferred from SIO1 to the buffer RAM, and the automatic data transmit/receive address pointer (ADTP) is decremented. Then transmit data 2 (T2) is transferred from the buffer RAM to SIO1. (ii) 4th byte transmission/reception point (refer to Figure 14-10 (b)) Transmission/reception of the third byte is completed, and transmit data 4 (T4) is transferred from the buffer RAM to SIO1. When transmission of the fourth byte is completed, receive data 4 (R4) is transferred from SIO1 to the buffer RAM, and ADTP is decremented. (iii) Completion of transmission/reception (refer to Figure 14-10 (c)) When transmission of the sixth byte is completed, receive data 6 (R6) is transferred from SIO1 to the buffer RAM, and the interrupt request flag (CSIIF1) is set (INTCSI1 generation). Figure 14-10. Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmission/Reception Mode) (1/2) (a) Before transmission/reception
FAFFH
FAC5H
Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3)
Receive data 1 (R1)
SIO1
5 Transmit data 4 (T4) Transmit data 5 (T5) FAC0H Transmit data 6 (T6) 0 --1
ADTP
CSIIF1
User's Manual U11302EJ4V0UM
281
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
Figure 14-10. Buffer RAM Operation in 6-Byte Transmission/Reception (in Basic Transmission/Reception Mode) (2/2) (b) 4th byte transmission/reception point
FAFFH
FAC5H
Receive data 1 (R1) Receive data 2 (R2) Receive data 3 (R3)
Receive data 4 (R4)
SIO1
2 Transmit data 4 (T4) Transmit data 5 (T5) FAC0H Transmit data 6 (T6) 0 --1
ADTP
CSIIF1
(c) Completion of transmission/reception
FAFFH
FAC5H
Receive data 1 (R1) Receive data 2 (R2) Receive data 3 (R3) 0 Receive data 4 (R4) Receive data 5 (R5)
SIO1
ADTP
FAC0H
Receive data 6 (R6)
1
CSIIF1
282
User's Manual U11302EJ4V0UM
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
(b) Basic transmission mode In this mode, the specified number of 8-bit unit data are transmitted. Serial transfer is started when any data is written to serial I/O shift register 1 (SIO1) while bit 7 (CSIE1) of serial operating mode register 1 (CSIM1) is set to 1. Upon completion of transmission of the last byte, the interrupt request flag (CSIIF1) is set. However, the termination of automatic transmission/reception should be judged by bit 3 (TRF) of the automatic data transmit/receive control register (ADTC), not CSIIF1. If a receive operation, busy control, and strobe control are not executed, the P20/SI1, P23/STB, and P24/BUSY pins can be used as normal I/O ports. Figure 14-11 shows the basic transmission mode operation timing, and Figure 14-12 shows the operation flowchart. The operation of the buffer RAM to transmit 6-byte data in transmission mode is shown in Figure 14-13. Figure 14-11. Basic Transmission Mode Operation Timing
Interval SCK1 SO1 CSIIF1 TRF D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Cautions 1. Because, in the basic transmission mode, the automatic transmit/receive function reads data from the buffer RAM after 1-byte transmission, an interval is inserted until the next transmission. As the buffer RAM read is performed at the same time as CPU processing, the maximum interval is dependent upon CPU processing and the value of the automatic data transmit/receive interval specification register (ADTI) (see (5) Automatic transmit/receive interval). 2. When TRF is cleared, the SO1 pin becomes low level. Remark CSIIF1: Interrupt request flag TRF: Bit 3 of the automatic data transmit/receive control register (ADTC)
User's Manual U11302EJ4V0UM
283
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
Figure 14-12. Basic Transmission Mode Flowchart
Start
Write transmit data in buffer RAM
Set ADTP to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes
Software execution
Set the transmission/reception operation interval time in ADTI
Write any data to SIO1 (Start trigger)
Write transmit data from buffer RAM to SIO1
Decrement pointer value
Transmission operation Hardware execution
Pointer value = 0
No
Yes
TRF = 0
No Software execution
Yes End
ADTP: Automatic data transmit/receive address pointer ADTI: SIO1: TRF: Automatic data transmit/receive interval specification register Serial I/O shift register 1 Bit 3 of the automatic data transmit/receive control register (ADTC)
284
User's Manual U11302EJ4V0UM
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
In 6-byte transmission (ARLD = 0, RE = 0) in basic transmission mode, buffer RAM operates as follows. (i) Before transmission (refer to Figure 14-13 (a)) After arbitrary data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1. When transmission of the first byte is completed, the automatic data transmit/receive address pointer (ADTP) is decremented. Then transmit data 2 (T2) is transferred from the buffer RAM to SIO1. (ii) 4th byte transmission point (refer to Figure 14-13 (b)) Transmission of the third byte is completed, and transmit data 4 (T4) is transferred from the buffer RAM to SIO1. When transmission of the fourth byte is completed, ADTP is decremented. (iii) Completion of transmission (refer to Figure 14-13 (c)) When transmission of the sixth byte is completed, the interrupt request flag (CSIIF1) is set (INTCSI1 generation). Figure 14-13. Buffer RAM Operation in 6-Byte Transmission (in Basic Transmission Mode) (1/2) (a) Before transmission
FAFFH
FAC5H
Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) 5 Transmit data 4 (T4) Transmit data 5 (T5) --1
SIO1
ADTP
FAC0H
Transmit data 6 (T6)
0
CSIIF1
User's Manual U11302EJ4V0UM
285
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
Figure 14-13. Buffer RAM Operation in 6-Byte Transmission (in Basic Transmission Mode) (2/2) (b) 4th byte transmission point
FAFFH
FAC5H
Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) 2 Transmit data 4 (T4) Transmit data 5 (T5) --1
SIO1
ADTP
FAC0H
Transmit data 6 (T6)
0
CSIIF1
(c) Completion of transmission
FAFFH
FAC5H
Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) 0 Transmit data 4 (T4) Transmit data 5 (T5)
SIO1
ADTP
FAC0H
Transmit data 6 (T6)
1
CSIIF1
286
User's Manual U11302EJ4V0UM
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
(c) Repeat transmission mode In this mode, data stored in the buffer RAM is transmitted repeatedly. Serial transfer is started by writing any data to serial I/O shift register 1 (SIO1) while bit 7 (CSIE1) of serial operating mode register 1 (CSIM1) is set to 1. Unlike the basic transmission mode, after the last byte (data in address FAC0H) has been transmitted, the interrupt request flag (CSIIF1) is not set, the value at the time the transmission was started is set in the automatic data transmit/receive address pointer (ADTP) again, and the buffer RAM contents are transmitted again. When a reception operation, busy control, and strobe control are not performed, the P20/SI1, P23/ STB, and P24/BUSY pins can be used as normal I/O ports. The repeat transmission mode operation timing is shown in Figure 14-14, and the operation flowchart in Figure 14-15. The operation of the buffer RAM to transmit 6-byte data in repeat transmission mode is shown in Figure 14-16. Figure 14-14. Repeat Transmission Mode Operation Timing
Interval SCK1 SO1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 Interval
Caution Since, in the repeat transmission mode, a read is performed on the buffer RAM after the transmission of one byte, the interval is included in the period up to the next transmission. As the buffer RAM read is performed at the same time as CPU processing, the maximum interval is dependent upon the CPU operation and the value of the automatic data transmit/receive interval specification register (ADTI) (see (5) Automatic transmit/receive interval).
User's Manual U11302EJ4V0UM
287
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
Figure 14-15. Repeat Transmission Mode Flowchart
Start
Write transmit data in buffer RAM
Set ADTP to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes
Software execution
Set the transmission/reception operation interval time in ADTI
Write any data to SIO1 (Start trigger)
Write transmit data from buffer RAM to SIO1
Decrement pointer value
Transmission operation
Hardware execution Pointer value = 0 No
Yes
Reset ADTP
ADTP: Automatic data transmit/receive address pointer ADTI: SIO1: Automatic data transmit/receive interval specification register Serial I/O shift register 1
288
User's Manual U11302EJ4V0UM
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
When data of 6 bytes are transmitted in repeat transmission mode (ARLD = 1, RE = 0), the buffer RAM operates as follows. (i) Before transmission (refer to Figure 14-16 (a)) After arbitrary data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1. When transmission of the first byte is completed, the automatic data transmit/receive address pointer (ADTP) is decremented. Then transmit data 2 (T2) is transferred from the buffer RAM to SIO1. (ii) Upon completion of transmission of 6 bytes (refer to Figure 14-16 (b)) When transmission of the sixth byte is completed, the interrupt request flag (CSIIF1) is not set. The first pointer value is set again to ADTP. (iii) 7th byte transmission point (refer to Figure 14-16 (c)) Transmit data 1 (T1) is transferred from the buffer RAM to SIO1 again. When transmission of the first byte is completed, ADTP is decremented. Then transmit data 2 (T2) is transferred from the buffer RAM to SIO1. Figure 14-16. Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmission Mode) (1/2) (a) Before transmission
FAFFH
FAC5H
Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) 5 Transmit data 4 (T4) Transmit data 5 (T5) --1
SIO1
ADTP
FAC0H
Transmit data 6 (T6)
0
CSIIF1
User's Manual U11302EJ4V0UM
289
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
Figure 14-16. Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmission Mode) (2/2) (b) Upon completion of transmission of 6 bytes
FAFFH
FAC5H
Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) 0 Transmit data 4 (T4) Transmit data 5 (T5)
SIO1
ADTP
FAC0H
Transmit data 6 (T6)
0
CSIIF1
(c) 7th byte transmission point
FAFFH
FAC5H
Transmit data 1 (T1) Transmit data 2 (T2) Transmit data 3 (T3) 5 Transmit data 4 (T4) Transmit data 5 (T5) --1
SIO1
ADTP
FAC0H
Transmit data 6 (T6)
0
CSIIF1
290
User's Manual U11302EJ4V0UM
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
(d) Automatic transmission/reception suspension and restart Automatic transmission/reception can be temporarily suspended by resetting bit 7 (CSIE1) of serial operating mode register 1 (CSIM1) to 0. If 8-bit data transfer is in progress, the transmission/reception is not suspended if bit 7 (CSIE1) is reset to 0. It is suspended upon completion of 8-bit data transfer. When suspended, bit 3 (TRF) of the automatic data transmit/receive control register (ADTC) is set to 0 after transfer of the 8th bit, and all the port pins used alternately as serial interface pins (P20/ SI1, P21/SO1, P22/SCK1, P23/STB, and P24/BUSY) are set to the port mode. To resume automatic transmission/reception, set CSIE1 to 1 and write any value to serial I/O shift register 1 (SIO1). This enables transmission of the remaining data. Cautions 1. If the HALT instruction is executed during automatic transmission/reception, transfer is suspended and the HALT mode is set even during 8-bit data transfer. When the HALT mode is cleared, automatic transmission/reception is restarted at the suspended point. 2. When suspending automatic transmission/reception, do not change the operating mode to 3-wire serial I/O mode while TRF = 1. Figure 14-17. Automatic Transmission/Reception Suspension and Restart
CSIE1 = 0 (Suspend command) Suspend Restart command CSIE1 = 1, Write to SIO1
SCK1 SO1 SI1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
CSIE1: Bit 7 of serial operating mode register 1 (CSIM1)
User's Manual U11302EJ4V0UM
291
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
(4) Synchronization control Busy control and strobe control are used to synchronize transmission/reception data between the master device and slave device. By using these functions, a bit slippage in data being transmitted/received can be detected. (a) Busy control option Busy control is used to allow a slave device to output a busy signal to the master device, so that the master device puts serial transmission/reception into a wait state while the busy signal is active. To use the busy control option, the following conditions must be satisfied. * Set bit 5 (ATE) of serial operating mode register 1 (CSIM1) to 1. * Set bit 1 (BUSY1) of the automatic data transmit/receive control register (ADTC) to 1. Figure 14-18 shows the system configuration of the master device and a slave device when the busy control option is used. Figure 14-18. System Configuration with Busy Control Option
Master device ( PD780208 Subseries) SCK1 SO1 SI1 BUSY
Slave device SCK1 SO1 SI1
The master device inputs the busy signal output by the slave device to the BUSY/P24 pin. It samples the input busy signal in synchronization with the fall of the serial clock. Even if the busy signal becomes active while 8-bit data is being transmitted or received, transmission/reception is not put into a wait state. If the busy signal is active at the rising edge of the serial clock two clocks after transmission or reception of 8-bit data has been completed, the busy signal becomes valid. After that, transmission or reception is put into a wait state while the busy signal is active. The active level of the busy signal is specified by bit 0 (BUSY0) of ADTC, as follows. BUSY0 = 0: Active high BUSY0 = 1: Active low When using the busy control option, select the internal clock as the serial clock. Busy control cannot be executed with an external clock. Figure 14-19 shows the operation timing when using the busy control option. Caution Busy control cannot be executed when the interval time is controlled by using the automatic data transmit/receive interval specification register (ADTI). If an attempt is made to execute both control operations at the same time, busy control is invalid.
292
User's Manual U11302EJ4V0UM
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
Figure 14-19. Operation Timing When Using Busy Control Option (BUSY0 = 0)
SCK1
SO1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SI1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
BUSY Wait CSIIF1 Busy input clear Busy input valid TRF
Caution
When TRF is cleared, the SO1 pin becomes low level.
Remark CSIIF1: Interrupt request flag TRF: Bit 3 of the automatic data transmit/receive control register (ADTC)
When the busy signal becomes inactive, the wait is cleared. If the sampled busy signal is inactive, transmission/reception of the next 8-bit data is started at the falling edge of the next serial clock. Note that, because the busy signal is asynchronous to the serial clock, it takes the master device up to 1 clock to sample the busy signal even if the slave device has made the busy signal inactive. In addition, it takes 0.5 clock until data transfer is started after the signal has been sampled. To clear the wait, therefore, it is necessary for the slave device to keep the busy signal inactive for at least 1.5 clocks. Figure 14-20 shows the timing of the busy signal and wait clearance. In Figure 14-20, the busy signal becomes active as soon as transmission/reception has started. Figure 14-20. Busy Signal and Clearing Wait (BUSY0 = 0)
SCK1
SO1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SI1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
BUSY (active high)
1.5 clocks (min.) If busy signal becomes inactive immediately after it has been sampled. Wait Busy input clear Busy input valid
User's Manual U11302EJ4V0UM
293
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
(b) Busy & strobe control option Strobe control is used to synchronize data transmission/reception between the master device and a slave device. The master device outputs a strobe signal from the STB/P23 pin on completion of transmission/reception of 8-bit data. This strobe signal informs the slave device of the data transmission/reception completion timing of the master device. Therefore, synchronization can be established even if bit slippage occurs due to noise carried on the serial clock, keeping bit slippage from affecting transmission of the next byte. To use the strobe control option, the following conditions must be satisfied. * Set bit 5 (ATE) of serial operating mode register 1 (CSIM1) to 1. * Set bit 2 (STRB) of the automatic data transmit/receive control register (ADTC) to 1. Usually, the busy control and strobe control options are simultaneously used for handshaking. In this case, the strobe signal is output from the STB/P23 pin and the BUSY/P24 pin is sampled. While a busy signal is being input to the pin, transmission/reception can be put into a wait state. If strobe control is not executed, the P23/STB pin can be used as a normal I/O port pin. Figure 14-21 shows the operation timing when using the busy & strobe control option. When the strobe control option is used, the interrupt request flag (CSIIF1) that is set on completion of transmission/reception is set after the strobe signal has been output. Figure 14-21. Operation Timing When Using Busy & Strobe Control Option (BUSY0 = 0)
SCK1
SO1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SI1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
STB
BUSY
CSIIF1 Busy input clear Busy input valid TRF
Caution
When TRF is cleared, the SO1 pin becomes low level.
Remark CSIIF1: Interrupt request flag TRF: Bit 3 of the automatic data transmit/receive control register (ADTC)
294
User's Manual U11302EJ4V0UM
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
(c) Bit slippage detection function with busy signal During automatic transmission/reception, bit slippage may take place in the serial clock of the slave device due to the noise carried on the serial clock signal output by the master device. Unless the strobe control option is used at this time, the bit slippage affects transmission of the next byte. In such a case, the master device can detect the bit slippage by using the busy control option and checking the busy signal during transmission. The bit slippage is detected by using the busy signal as follows. The slave outputs a busy signal after the 8th rise of the serial clock during data transmission/reception (at this time, make the busy signal inactive within two clocks to stop the master device putting transmission/reception into a wait state). The master samples the busy signal in synchronization with the fall of the serial clock. If bit slippage does not occur, the busy signal is found to be inactive after it has been sampled eight times. If the busy signal is found to be active when it has been sampled, it is assumed that bit slippage has occurred, and error processing is performed (by setting bit 4 (ERR) of the automatic data transmit/ receive control register (ADTC) to 1). Figure 14-22 shows the operation timing of the bit slippage detection function using the busy signal. Figure 14-22. Operation Timing of Bit Slippage Detection Function Using Busy Signal (BUSY0 = 1)
SCK1 (Master side) Bit slippage due to noise SCK1 (Slave side)
SO1
D7 D6 D5 D4 D3 D2 D1 D0
D7
D7 D6 D5 D4 D3 D2 D1
D0
SI1
D7 D6 D5 D4 D3 D2 D1 D0
D7
D7 D6 D5 D4 D3 D2 D1
D0
BUSY
CSIIF1
CSIE1
ERR No busy detection Error interrupt request generation Error detection
CSIIF1: Interrupt request flag CSIE1: Bit 7 of serial operating mode register 1 (CSIM1) ERR: Bit 4 of the automatic data transmit/receive control register (ADTC)
User's Manual U11302EJ4V0UM
295
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
(5) Automatic transmit/receive interval When the automatic transmit/receive function is used, one byte is transmitted/received and then the buffer RAM is read/written; therefore an interval is inserted before the next transmission/reception. When the automatic transmit/receive function is performed using an internal clock, since the read/write operations from/to the buffer RAM are done in parallel with CPU processing, the interval depends on the CPU processing at the timing of the serial clock's eighth rising-edge and the value set in the automatic data transmit/receive interval specification register (ADTI). Whether or not the interval depends on ADTI can be selected by setting bit 7 (ADTI7) of ADTI. When ADTI7 is set to 0, the interval depends only on the CPU processing. When ADTI7 is set to 1, the interval is the value determined by the contents of ADTI or other value determined by CPU processing, whichever is greater. When the automatic transmit/receive function is performed using an external clock, the clock must be selected so that the interval is longer than the value shown in (b). Figure 14-23. Automatic Transmit/Receive Interval
Interval SCK1 SO1 SI1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
CSIIF1
CSIIF1: Interrupt request flag
296
User's Manual U11302EJ4V0UM
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
(a) When automatic transmit/receive function is performed using an internal clock The internal clock operation is selected when bit 1 (CSIM11) of serial operating mode register 1 (CSIM1) is set to 1. In this case, the interval is determined as follows by CPU processing. When bit 7 (ADTI7) of the automatic data transmit/receive interval specification register (ADTI) is set to 0, the interval is determined by CPU processing. When ADTI7 is set to 1, the interval is determined by the contents of ADTI or by CPU processing, whichever is greater. For the interval determined by ADTI, see Figure 14-5 Format of Automatic Data Transmit/Receive Interval Specification Register. Table 14-3. Interval Determined by CPU Processing (with Internal Clock Operation)
CPU Processing When using multiplication instruction When using division instruction External access 1-wait mode Other than above
Interval MAX. (2.5TSCK, 13TCPU) MAX. (2.5TSCK, 20TCPU) MAX. (2.5TSCK, 9TCPU) MAX. (2.5TSCK, 7TCPU)
TSCK: fSCK: TCPU: fCPU:
1/fSCK Serial clock frequency 1/fCPU CPU clock (set by bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC))
MAX. (a, b) : a or b, whichever is greater Figure 14-24. Operation Timing When Automatic Transmit/Receive Function Is Operating with Internal Clock
fX TCPU fCPU (n = 1) TSCK SCK1 SO1 SI1 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Interval
fX:
Main system clock oscillation frequency
fCPU: CPU clock (set by bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC)) TCPU: 1/fCPU TSCK: 1/fSCK fSCK: Serial clock frequency
User's Manual U11302EJ4V0UM
297
CHAPTER 14
SERIAL INTERFACE CHANNEL 1
(b) When automatic transmit/receive function is performed using an external clock The external clock operation is selected when bit 1 (CSIM11) of serial operating mode register 1 (CSIM1) is cleared to 0. When the automatic transmit/receive function is performed using an external clock, the clock must be selected so that the interval is longer than the values shown below. Table 14-4. Interval Determined by CPU Processing (with External Clock Operation)
CPU Processing When using multiplication instruction When using division instruction External access 1-wait mode Other than above
Interval 13TCPU or more 20TCPU or more 9TCPU or more 7TCPU or more
TCPU: 1/fCPU fCPU: CPU clock (set by bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC))
298
User's Manual U11302EJ4V0UM
CHAPTER 15 VFD CONTROLLER/DRIVER
15.1
VFD Controller/Driver Functions
The functions of the VFD controller/driver incorporated in the PD780208 Subseries are as follows. (1) Automatically outputs the segment signals (DMA operation) and digit signals by automatically reading data displayed. (2) Controls 9- to 40-segment and 2- to 16-digit VFDs (vacuum fluorescent display) using display mode registers 0, 1, and 2 (DSPM0 to DSPM2). (3) Digit signal output timing can be specified freely by selecting display mode 2 using display mode register 0 (DSPM0). (4) Pins not used for VFD display can be used as output and I/O ports (but FIP0 to FIP12 are display outputonly pins). (5) Luminance can be adjusted in 8 levels using display mode register 1 (DSPM1). (6) Incorporates hardware for key scan application. * Generates interrupt signal (INTKS) indicating key scan timing. * Outputs key scan signals from segment output pins by setting key scan data to port 8 through port 12. * Detects timing at which key scan data are output by the key scan flag (KSF). (7) Incorporates a high-withstanding-voltage output buffer that can directly drive the VFD. (8) The display output pins can be connected to on-chip pull-down resistors by mask option. Cautions 1. This cannot be used with the subsystem clock. To stop the main oscillation, stop the display in advance by setting bits 4 to 7 (DIGS0 to DIGS3) of display mode register 1 (DSPM1) to 0000. 2. Set ports 8 through 12 to 0 and output latches to 0 before doing the following: * Using the VFD controller/driver * Stopping display
User's Manual U11302EJ4V0UM
299
CHAPTER 15
VFD CONTROLLER/DRIVER
Figure 15-1. VFD Controller Operation Timing in Display Mode 1 (DSPM05 = 0)
TCYT TDSP Digit signal FIP0 FIP1 FIP2 . . . . . . . . . . . . FIPn TKS
TDIG
Key scan flag (KSF) Can be changed whenever necessary Segment signalNote
1 display cycle
Key scan timing
DSPM05: Bit 5 of display mode register 0 (DSPM0) n: TDSP: TKS: TCYT: TDIG: Note Displayed digits - 1 (Digits 2 to 16 can be selected using display mode register 1 (DSPM1)) 1 display cycle (1024/fx (204.8 s: @ 5.0 MHz operation) or 2048/fx (409.6 s: @ 5.0 MHz operation)) Key scan timing (TKS = TDSP) Display cycle (TCYT = TDSP x (Displayed digits + 1)) Pulse width of digit signal (Can be selected from 8 types using DSPM1) The user can select the cut width of the segment signals by setting bits 1 to 3 (DIMS1 to DIMS3) of DSPM1. Therefore, actual output waveforms may be different from the above illustration and have the cut widths shown in Figure 15-6. Remark If DSPM05 is set to 1, digit signals are output according to the values set in the display RAM.
300
User's Manual U11302EJ4V0UM
CHAPTER 15
VFD CONTROLLER/DRIVER
There are 53 display output pins. Of these, 40 pins, FIP13 to FIP52, have alternate port functions. These pins are used as port pins when display stop is set using bits 4 to 7 (DIGS0 to DIGS3) of display mode register 1 (DSPM1). Even when display is enabled, display output pins not used for outputting digit signals and segment signals can be used as port pins. Table 15-1. Relationship Between Display Output Pins and Port Pins
Display Pin Name FIP13 to FIP20 FIP21 to FIP28 FIP29 to FIP36 FIP37 to FIP44 FIP45 to FIP52
Alternate Port Name P80 to P87 P90 to P97 P100 to P107 P110 to P117 P120 to P127
I/O For output port
For output port
I/O port
I/O port
I/O port
15.2
VFD Controller/Driver Configuration
The VFD controller/driver consists of the following hardware. Table 15-2. VFD Controller/Driver Configuration
Item Display output Control registers
Configuration 53 pins (segments: 9 to 40, digits: 2 to 16) Display mode register 0 (DSPM0) Display mode register 1 (DSPM1) Display mode register 2 (DSPM2)
User's Manual U11302EJ4V0UM
301
302
0 0 5 Write mask controller Display data memory
User's Manual U11302EJ4V0UM
Figure 15-2. VFD Controller/Driver Block Diagram
Internal bus Display mode register 2 (DSPM2) USEG5 USEG4 USEG3 USEG2 USEG1 USEG0 Display mode register 1 (DSPM1) DIGS3 DIGS2 DIGS1 DIGS0 DIMS3 DIMS2 DIMS1 DIMS0 Display mode register 0 (DSPM0) KSF DSPM06 DSPM05 SEGS4 SEGS3 SEGS2 SEGS1 SEGS0
4 Display timing selector
3
Display cycle
5
CHAPTER 15
Digit signal generator
Blanking signal generator
VFD CONTROLLER/DRIVER
Display data selector
Display data latch
Port output latch
High-withstanding-voltage output buffer
FIP0
FIP13/P80
FIP52/P127
CHAPTER 15
VFD CONTROLLER/DRIVER
15.3
VFD Controller/Driver Control Registers
15.3.1 Control registers There are three registers for controlling the VFD controller/driver. * Display mode register 0 (DSPM0) * Display mode register 1 (DSPM1) * Display mode register 2 (DSPM2) (1) Display mode register 0 (DSPM0) (see Figure 15-3) This register sets the following and displays the display timing/key scan state. * Display mode * Display segment number/display output total number * Mode for subsystem clock noise eliminator DSPM0 is set with an 8-bit memory manipulation instruction. However, only bit 7 (KSF) can be read with a 1-bit memory manipulation instruction. RESET input sets DSPM0 to 00H. (2) Display mode register 1 (DSPM1) (see Figure 15-4) This register sets the following. * Display digit number/display pattern number * Cut width of the VFD output signal * Display cycle (TDSP) When bit 0 (DIMS0) is set to 1 and the display cycle to 2048/fx (409.6 s: @ 5.0 MHz operation), light leakage is reduced. As the display cycle approaches the commercial power supply frequency when the display digits are increased, the display will flicker. In this case, select 1024/fx (204.8 s: @ 5.0 MHz operation). If light leaks, adjust the cut width of the digit signal using bits 1 to 3 (DIMS1 to DIMS3). DSPM1 is set with an 8-bit memory manipulation instruction. RESET input sets DSPM1 to 00H.
User's Manual U11302EJ4V0UM
303
CHAPTER 15
VFD CONTROLLER/DRIVER
(3) Display mode register 2 (DSPM2) (see Figure 15-5) DSPM2 is the register that holds the number of mask bits in the display data storage area when display mode 2 (DSPM05 = 1) is selected by display mode register 0 (DSPM0). By using this register to mask the part of the display data that does not need to be rewritten, the software workload is reduced. Mask bits are assigned from S0 (= the least significant bit of the lowest address in the display output area defined by bits 0 to 4 of DSPM0). DSPM2 is set with an 8-bit memory manipulation instruction. RESET input sets DSPM2 to 00H. The following illustration shows the status of the display data memory when the number of segments is 32 and the number of mask bits is 11.
11 bits S31 ....................... S24 S23 ................... S16 S15 .................... S8 FA70H FA60H FA50H S7 .................... S0 FA40H
Bit 7
07
07
07
0
: The shaded part shows the area in which display data is rewritable during display
: The slashed part shows the area in which display data is not rewritable during display (display data are fixed)
Caution The number of mask bits specified must be below the total number of display outputs defined by display mode register 0 (DSPM0).
304
User's Manual U11302EJ4V0UM
CHAPTER 15
VFD CONTROLLER/DRIVER
Figure 15-3. Format of Display Mode Register 0 (1/2)
Symbol DSPM0
7
6
5
4
3
2
1
0
Address FFA0H
After reset 00H
R/W R/W
KSF DSPM06 DSPM05 SEGS4 SEGS3 SEGS2 SEGS1 SEGS0
R/W SEGS4 SEGS3 SEGS2 SEGS1 SEGS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Display segment (display mode 1) 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38Note 39Note 40Note
Display output total (display mode 2) 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Note
When the total number of digits and segments together exceeds 53, the digits have priority.
User's Manual U11302EJ4V0UM
305
CHAPTER 15
VFD CONTROLLER/DRIVER
Figure 15-3. Format of Display Mode Register 0 (2/2)
Symbol DSPM0 7 6 5 4 3 2 1 0 Address FFA0H After reset 00H R/W R/WNote 1
KSF DSPM06 DSPM05 SEGS4 SEGS3 SEGS2 SEGS1 SEGS0
R/W DSPM05 Display mode setting 0 1 Display mode 1 (Segment/character type) Display mode 2 (Type in which a segment spans over two or more grids.)
R/W DSPM06 Subsystem clock noise eliminator mode settingNote 2 0 1 2.5 MHz < fX 5.0 MHz 1.25 MHz fX 2.5 MHzNote 3
R
KSF 0 1
Timing state Display timing Key scan timing
Notes 1. Bit 7 (KSF) is a read-only bit. 2. Set the values according to the main system clock oscillation frequency (fX) used. The noise eliminator is enabled during VFD display operations. 3. If fX selected is between 1.25 MHz and 2.5 MHz, set DSPM06 to 1 prior to VFD display. Caution When a main system clock frequency below 1.25 MHz is selected and the VFD controller/ driver is used, make sure to use the main system clock for watch timer counting by setting TCL24 to 0.
306
User's Manual U11302EJ4V0UM
CHAPTER 15
VFD CONTROLLER/DRIVER
Figure 15-4. Format of Display Mode Register 1
Symbol
7
6
5
4
3
2
1
0
Address FFA1H
After reset 00H
R/W R/W
DSPM1 DIGS3 DIGS2 DIGS1 DIGS0 DIMS3 DIMS2 DIMS1 DIMS0
DIMS0 0 1
Display mode cycle setting 1024/fX is 1 display cycle. (1 display cycle = 204.8 s: when operated at 5.0 MHz) 2048/fX is 1 display cycle. (1 display cycle = 409.6 s: when operated at 5.0 MHz)
DIMS3 DIMS2 DIMS1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
VFD output signal cut width 1/16 2/16 4/16 6/16 8/16 10/16 12/16 14/16
DIGS3 DIGS2 DIGS1 DIGS0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Display digit (display mode 1) DSPM05 = 0 Display stopped (static display) 2 digits 3 digits 4 digits 5 digits 6 digits 7 digits 8 digits 9 digits 10 digits 11 digits 12 digits 13 digits 14 digits 15 digits 16 digits
Note
Display pattern (display mode 2) DSPM05 = 1 Display stopped (static display)Note 2 patterns 3 patterns 4 patterns 5 patterns 6 patterns 7 patterns 8 patterns 9 patterns 10 patterns 11 patterns 12 patterns 13 patterns 14 patterns 15 patterns 16 patterns
Note
Static display is possible when display stop is selected, by manipulating the port output latch. Main system clock oscillation frequency
Remark fX:
DSPM05: Bit 5 of display mode register 0 (DSPM0)
User's Manual U11302EJ4V0UM
307
CHAPTER 15
VFD CONTROLLER/DRIVER
Figure 15-5. Format of Display Mode Register 2 (1/2)
Symbol DSPM2 7 0 6 0 5 4 3 2 1 0 Address FFA2H After reset 00H R/W R/W
USEG5 USEG4 USEG3 USEG2 USEG1 USEG0
USEG5 USEG4 USEG3 USEG2 USEG1 USEG0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Number of mask bits to be written None 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
308
User's Manual U11302EJ4V0UM
CHAPTER 15
VFD CONTROLLER/DRIVER
Figure 15-5. Format of Display Mode Register 2 (2/2)
Symbol DSPM2 7 0 6 0 5 4 3 2 1 0 Address FFA2H After reset 00H R/W R/W
USEG5 USEG4 USEG3 USEG2 USEG1 USEG0
USEG5 USEG4 USEG3 USEG2 USEG1 USEG0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Number of mask bits to be written 32 33 34 35 36 37 38 39 Setting prohibited
Other than the above
User's Manual U11302EJ4V0UM
309
CHAPTER 15
VFD CONTROLLER/DRIVER
15.3.2 One-display period and cut width The digit signal is equally cut at the beginning and end of the display period by the cut width set by bits 1 to 3 (DIMS1 to DIMS3) of display mode register 1 (DSPM1). Figure 15-6. Cut Width of Segment/Digit Signal
1 display cycle = TDSP 1/16 1/16
Segment signal Digit signal (1/16 of cut width) 1/8 1/8
Segment signal Digit signal (2/16 of cut width) 1/4 1/4
Segment signal Digit signal (4/16 of cut width)
0 is output for the first one-display cycle when display is started from the display stop status. Figure 15-7. VFD Controller Display Start Timing
TDSP
Digit signal FIP0 FIP1 FIP2
TKS
TDIG
FIPn Key scan flag (KSF) Can be changed whenever necessary Segment signalNote
Displaying starts
1 display cycle
Key scan timing
n: TDSP: TKS: TDIG: Note
Displayed digits - 1 (Digits 2 to 16 can be selected using display mode register 1 (DSPM1)) 1 display cycle (1024/fx (204.8 s: @ 5.0 MHz operation) or 2048/fx (409.6 s: @ 5.0 MHz operation)) Key scan timing (TKS = TDSP) Pulse width of digit signal (Can be selected from 8 types using DSPM1) The user can select the cut width of the segment signals by setting bits 1 to 3 (DIMS1 to DIMS3) of DSPM1. Therefore, actual output waveforms may be different from the above illustration and have the cut widths shown in Figure 15-6.
310
User's Manual U11302EJ4V0UM
CHAPTER 15
VFD CONTROLLER/DRIVER
15.4
Selecting Display Mode
The number of segments and digits displayed by the VFD controller/driver depends on the display mode set. Figure 15-8. Selection of Display Mode
Number of digits selected 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0
9 10 11 12 13 14 15 16
Number of segments selected
17 18 19 20 21 22 23
36 37 38 39 40
Caution When the total number of digits and segments together exceeds 53, the digits have priority.
User's Manual U11302EJ4V0UM
311
CHAPTER 15
VFD CONTROLLER/DRIVER
15.5
Display Mode and Display Output
The on-chip VFD controller/driver assigns pins FIP0 to FIP52/P127 to digit signals and segment signals (in this order). The number assigned is specified by display mode registers 0 and 1 (DSPM0 and DSPM1). The remaining pins are assigned as general-purpose ports. The pin configuration for a 14-segment display is shown below as an example. Figure 15-9. Pin Configuration for 14-Segment Display
Number of display digits selected Display stop FIP0 FIP1 FIP2 FIP3 FIP4 FIP5 FIP6 FIP7 FIP8 FIP9 FIP10 FIP11 FIP12 P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 P97 P100 P101 P102 2 T0 T1 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 P97 P100 P101 P102 3 T0 T1 T2 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 P97 P100 P101 P102 4 T0 T1 T2 T3 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 P97 P100 P101 P102 ............... ............... 14 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 P97 P100 P101 P102 15 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 P100 P101 P102 16 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 P101 P102
Pin name FIP0 FIP1 FIP2 FIP3 FIP4 FIP5 FIP6 FIP7 FIP8 FIP9 FIP10 FIP11 FIP12 FIP13/P80 FIP14/P81 FIP15/P82 FIP16/P83 FIP17/P84 FIP18/P85 FIP19/P86 FIP20/P87 FIP21/P90 FIP22/P91 FIP23/P92 FIP24/P93 FIP25/P94 FIP26/P95 FIP27/P96 FIP28/P97 FIP29/P100 FIP30/P101 FIP31/P102
FIP51/P126 FIP52/P127
Remark T0 to T15: Display digit pins S0 to S13: Segment pins
...
P126 P127 P126 P127
...
P126 P127 P126 P127 P126 P127
P126 P127
...
P126 P127
312
User's Manual U11302EJ4V0UM
CHAPTER 15
VFD CONTROLLER/DRIVER
15.6
Display Data Memory
The display data memory is the area for storing the segment data to be displayed. This memory is mapped at addresses FA30H to FA7FH. To display data on the VFD, the VFD controller reads the data stored in this memory regardless of the type of operations performed by the CPU (DMA operations). The area not used for the display data can be used as normal RAM area. At the key scan timing (TKS), all segment outputs and digit outputs become "0" and the output latch data of ports 8, 9, 10, 11, and 12 are output to FIP37/P110 to FIP52/P127. Figure 15-10. Relationship Between Display Data Memory Contents and Segment Output
Bit 7 FA70H FA71H FA72H FA73H FA74H FA75H FA76H FA77H Display data memory FA78H FA79H FA7AH FA7BH FA7CH FA7DH FA7EH FA7FH
07 FA60H FA61H FA62H FA63H FA64H FA65H FA66H FA67H FA68H FA69H FA6AH FA6BH FA6CH FA6DH FA6EH FA6FH
07 FA50H FA51H FA52H FA53H FA54H FA55H FA56H FA57H FA58H FA59H FA5AH FA5BH FA5CH FA5DH FA5EH FA5FH
07 FA40H FA41H FA42H FA43H FA44H FA45H FA46H FA47H FA48H FA49H FA4AH FA4BH FA4CH FA4DH FA4EH FA4FH
07 FA30H FA31H FA32H FA33H FA34H FA35H FA36H FA37H FA38H FA39H FA3AH FA3BH FA3CH FA3DH FA3EH FA3FH
0 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 Timing output
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TKS
S39
S32 S31
S24 S23
S16 S15
S8 S7
S0
User's Manual U11302EJ4V0UM
313
CHAPTER 15
VFD CONTROLLER/DRIVER
15.7 Key Scan Flag and Key Scan Data
15.7.1 timing. KSF is mapped at bit 7 of display mode register 0 (DSPM0) and can be tested one bit at a time. It cannot be written. By testing the KSF, it can be determined if it is during the key scan timing and if the data input using keys is correct. 15.7.2 Key scan data Key scan flag
The key scan flag (KSF) is set to 1 during the key scan timing and reset automatically to 0 during the display
The data stored in ports 8, 9, 10, 11, and 12 are output from pins FIP13 to FIP52 at the key scan timing. By changing the data output from ports 11 and 12 during the key scan timing, key scan can be performed using these pins FIP13 to FIP52. Caution If, during the key scan timing, scanning is performed which causes both the segment and digit lines to turn ON at the same time, the display may be disturbed.
314
User's Manual U11302EJ4V0UM
CHAPTER 15
VFD CONTROLLER/DRIVER
15.8
Light Leakage of VFD
Light may leak when a VFD is driven using the PD780208 Subseries. Two possible causes are as follows. (1) Light leakage due to a short blanking time Figure 15-11 shows the signal waveforms when only the first digit of two digits to be displayed is lit. As shown in this figure, when the blanking time is short, the T1 signal rises before the segment signal disappears, resulting in light leakage. Generally, as approximately 20 s is required for the blanking time, consider the values set to display mode register 1 (DSPM1) carefully. Figure 15-11. Light Leakage due to Short Blanking Time
Blanking time
T0
T1
Light leakage S0
(2) Light leakage due to capacitance between segment and grid of VFD As shown in Figure 15-13, light may leak even if the blanking time is sufficient. As shown by CSG in Figure 15-12, as there is capacitance between the grid and segment of the VFD, the timing signal pin voltage will be increased via CSG when the segment signal turns on. As shown in Figure 15-13, when this voltage exceeds the cut-off voltage (EK), light will leak. This spike noise voltage depends on the size of CSG and the on-chip pull-down resistor (RL). The greater the value of CSG or the RL value, the greater the voltage, making it easy for light to leak. This CSG value differs according to the area of the data displayed on the VFD. The greater the area, the greater CSG. Consequently, pull-down resistor values with which light will not leak also depend on the size of the VFD. As the value of the pull-down resistor incorporated by the mask option is comparatively great, in some cases, light leakage cannot be controlled with resistance only. If the quality of the display is insufficient, increase the back bias (increase the EK), place a filter over the VFD, or attach a 10 k pull-down resistor externally to the timing signal pin.
User's Manual U11302EJ4V0UM
315
CHAPTER 15
VFD CONTROLLER/DRIVER
Depending on the duty cycle of the spike noise voltage for the whole display period, the ease with which light leaks due to CSG varies. The fewer the number of digits displayed, the easier it is for light to leak. Lowering the luminance of the display is also effective. Figure 15-12. Light Leakage due to CSG
PD780205
VDD +5V
S0 _ FIP T0 _ CSG Segment grid filament
RL
RL EK _30 V VLOAD
EK: Cut-off voltage RL: On-chip pull-down resistor
Figure 15-13. Waveform of Light Leakage due to CSG
T0
T1 EK
S0
316
User's Manual U11302EJ4V0UM
CHAPTER 15
VFD CONTROLLER/DRIVER
15.9 Display Examples
The PD780208 Subseries has a VFD controller/driver that enables the following three types of VFD display. Display types can be switched by setting bit 5 (DSPM05) of display mode register 0 (DSPM0). * Segment type (Display mode 1: DSPM05 = 0) * Dot type (Display mode 1: DSPM05 = 0) * Display type in which a segment spans two or more grids (Display mode 2: DSPM05 = 1) The following figures show VFD display examples for each display type. (1) Segment type: 10 segments x 11 digits
i
SUN
MON
TUE
j j
WED
THU
FRI
SAT
f e
a g d b c h
AM PM 0
i j
1
2
3
4
5
6
7
8
9
10
(2) Dot type: 35 segments x 16 digits
(3) Display type in which a segment spans two or more grids: 23 segments x 7 patterns
5G
4G
3G
2G
1G
r2 r3 300 q 250
Heating
h
2a 2f 2g 2e 2d 2c 1e 2b
Fast
i
1a 1f 1g 1c 1d 1b
Middle
j
n
Slow
h
2a 2f 2g 2e 2d 2c 2b
Start
i
1a 1f 1g 1e 1d 1c 1b
End
n j
Kcal
o p
r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14
o p
200
gC
m
150
k
l
m
k
l
Temp Defrost
Open
Preheat Keep Warm
Timer
100
User's Manual U11302EJ4V0UM
317
CHAPTER 15
VFD CONTROLLER/DRIVER
15.9.1 Segment type (display mode 1: DSPM05 = 0) Figure 15-14 shows the display data memory configuration and data reading order when the device controls a 10-segment x 11-digit VFD display. As "segment type" (display mode 1) is selected, the display data memory stores segment data. Figure 15-14. Display Data Memory Configuration and Segment Data Reading Order (Segment Type)
Bit 7
07 FA70H <1> <2> FA60H FA71H <3> FA72H FA73H FA74H FA75H FA76H FA61H FA62H FA63H FA64H FA65H FA66H FA67H FA68H FA69H FA6AH FA6BH FA6CH FA6DH FA6EH FA6FH
07 FA50H FA51H FA52H FA53H FA54H FA55H FA56H FA57H FA58H FA59H FA5AH FA5BH FA5CH FA5DH FA5EH FA5FH
07 FA40H FA41H FA42H FA43H FA44H FA45H FA46H FA47H FA48H FA49H FA4AH FA4BH FA4CH FA4DH FA4EH FA4FH
07 FA30H FA31H FA32H FA33H FA34H FA35H FA36H FA37H FA38H FA39H FA3AH FA3BH FA3CH FA3DH FA3EH FA3FH
0 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 TKS
Display data memory
FA77H FA78H FA79H FA7AH FA7BH FA7CH FA7DH FA7EH FA7FH
S9
S0
Remarks 1. <1> through <3> show the segment data reading order. 2. The shaded area shows the segment data storage area. In the case of example (1) in 15.9, the contents of the data memory indicated by shading are as shown in Figure 15-15.
318
User's Manual U11302EJ4V0UM
Figure 15-15. Relationship Between Display Data Memory Contents and Segment Outputs in 10-Segment x 11-Digit Display Mode
Display data memory FA7AH FA79H FA78H FA77H FA76H FA75H FA74H FA73H FA72H FA71H FA70H FA6AH FA69H FA68H FA67H FA66H FA65H FA64H FA63H FA62H FA61H FA60H 0 0 0 0 0 0 0 0 1 0
User's Manual U11302EJ4V0UM
0 1 1 0 0 0 0 0 0 0
0 1 1 0 0 0 0 0 1 0
0 0 0 0 0 0 0 0 0 1
0 1 1 0 0 1 1 0 0 0
1 0 1 1 0 1 1 0 0 0
0 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 0 0 0
1 1 1 1 0 0 1 0 0 0
0 0 0 1 1 0 1 0 0 0
0 0 1 0 1 1 1 0 0 0
Bit 7 Bit 6 Bit 5 Bit 4 FA7xH Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 FA6xH Bit 6
CHAPTER 15 VFD CONTROLLER/DRIVER
S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
T10
T9
T8
T7
T6
T5
T4
T3
T2
T1
T0
a
b
c
d
e
f
g
h
i
j
i AM PM 0 i j
SUN
MON
TUE j j
WED
THU
FRI
SAT
a fgb edc 10 h
1
2
3
4
5
6
7
8
9
319
CHAPTER 15
VFD CONTROLLER/DRIVER
15.9.2 Dot type (display mode 1: DSPM05 = 0) Figure 15-16 shows the display data memory configuration and data reading order when the device controls a 35-segment (5 x 7 dots) x 16-digit VFD display. As "dot type" (display mode 1) is selected, the display data memory stores segment data. Figure 15-16. Display Data Memory Configuration and Segment Data Reading Order (Dot Type)
Bit 7 FA70H <1> FA71H <6> FA72H FA73H FA74H FA75H FA76H Display data memory FA77H FA78H FA79H FA7AH FA7BH FA7CH FA7DH FA7EH FA7FH
07 FA60H <2> FA61H FA62H FA63H FA64H FA65H FA66H FA67H FA68H FA69H FA6AH FA6BH FA6CH FA6DH FA6EH FA6FH
07 FA50H <3> FA51H FA52H FA53H FA54H FA55H FA56H FA57H FA58H FA59H FA5AH FA5BH FA5CH FA5DH FA5EH FA5FH
07 FA40H <4> FA41H FA42H FA43H FA44H FA45H FA46H FA47H FA48H FA49H FA4AH FA4BH FA4CH FA4DH FA4EH FA4FH
07 <5> FA30H FA31H FA32H FA33H FA34H FA35H FA36H FA37H FA38H FA39H FA3AH FA3BH FA3CH FA3DH FA3EH FA3FH
0 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 TKS
S34
S0
Remarks 1. <1> through <6> show the segment data reading order. 2. The shaded area shows the segment data storage area. In the case of example (2) in 15.9, the contents of the data memory indicated by shading are as shown in Figure 15-17.
320
User's Manual U11302EJ4V0UM
CHAPTER 15
VFD CONTROLLER/DRIVER
Figure 15-17. Relationship Between Display Data Memory Contents and Segment Outputs in 35-Segment x 16-Digit Display Mode
Display data memory
FA7FH FA7EH FA7DH FA7CH FA7BH FA7AH FA79H FA78H FA77H FA76H FA75H FA74H FA73H FA72H FA71H FA70H FA6FH FA6EH FA6DH FA6CH FA6BH FA6AH FA69H FA68H FA67H FA66H FA65H FA64H FA63H FA62H FA61H FA60H FA5FH FA5EH FA5DH FA5CH FA5BH FA5AH FA59H FA58H FA57H FA56H FA55H FA54H FA53H FA52H FA51H FA50H FA4FH FA4EH FA4DH FA4CH FA4BH FA4AH FA49H FA48H FA47H FA46H FA45H FA44H FA43H FA42H FA41H FA40H FA3FH FA3EH FA3DH FA3CH FA3BH FA3AH FA39H FA38H FA37H FA36H FA35H FA34H FA33H FA32H FA31H FA30H S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S18 S17 S0 to S34 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 1 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 1 0 1 1 1 1 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 0 1 1 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 1 1 0 0 1 1 1 0 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 0 Bit 7 6 5 FA3xH FA4xH FA5xH FA6xH FA7xH
T15 T14 T13 T12 T11 T10
T9
T8
T7
T6
T5
T4
T3
T2
T1
T0
User's Manual U11302EJ4V0UM
321
CHAPTER 15
VFD CONTROLLER/DRIVER
15.9.3 Display type in which a segment spans two or more grids (display mode 2: DSPM05 = 1) In display mode 2, all of the display output data are stored in the display data memory. Figure 15-18 shows the display data RAM configuration and data reading order in a 23-segment x 5-grid display. Figure 15-18. Display Data Memory Configuration and Data Reading Order (Display Mode 2)
Bit 7
07 FA70H <1> FA71H <5> FA72H FA73H FA74H FA75H FA76H
07 FA60H <2> FA61H FA62H FA63H FA64H FA65H FA66H FA67H FA68H FA69H FA6AH FA6BH FA6CH FA6DH FA6EH FA6FH
07 FA50H <3> FA51H FA52H FA53H FA54H FA55H FA56H FA57H FA58H FA59H FA5AH FA5BH FA5CH FA5DH FA5EH FA5FH <4> FA40H FA41H FA42H FA43H FA44H FA45H FA46H FA47H FA48H FA49H FA4AH FA4BH FA4CH FA4DH FA4EH FA4FH
07 FA30H FA31H FA32H FA33H FA34H FA35H FA36H FA37H FA38H FA39H FA3AH FA3BH FA3CH FA3DH FA3EH FA3FH
0 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 TKS
Display data memory
FA77H FA78H FA79H FA7AH FA7BH FA7CH FA7DH FA7EH FA7FH
Remarks 1. <1> through <5> show the display output data reading order. 2. The slashed area shows the segment data storage area. 3. The shaded area shows the grid data storage area. In the case of example (3) in 15.9, the contents of the data memory areas indicated by shading and slashes are as shown in Figure 15-21. T0 through T6 in display mode 2 are for display patterns. Therefore, designate bits 4 to 7 (DIGS0 to DIGS3) of display mode register 1 (DSPM1) as 7 patterns, and bits 0 to 4 (SEGS0 to SEGS4) of display mode register 0 (DSPM0) as 28 display outputs in total. If there is some memory area where rewriting display output data is unnecessary, it should be masked by setting display mode register 2 (DSPM2).
322
User's Manual U11302EJ4V0UM
Figure 15-19. Segment Connection Example
P23 r1
P22 r2 j _
P21 q _ h _ h
P20 r8 n _ n _
P19 r9 o _ o _
P18 r10 p _ p _
P17 _ _ 2a _ 2a
P16 _ _ 2b _ 2b
P15 _ _ 2f _ 2f
P14 _ _ 2g _ 2g
P13 _ _ 2c _ 2c
P12 r13 m _
P11 r12
P10 r11 _ k
P9 _
P8 _ _ 1e
P7 r7 1c _
P6 r6
P5 r5 _ 1f
P4 r4 1b _
P3 r3
P2 _ _ 2d
P1 _ _ 2e _ 2e 1G 2G 3G 4G
CHAPTER 15
i j _ m _
l _ k
1d _ 1e 1c _
1g _ 1f 1b _
1a _ 2d
5G
User's Manual U11302EJ4V0UM
5G
4G
3G
2G r1
1G
VFD CONTROLLER/DRIVER
300 q 250
Heating
h 2a 2f 2g 2e 2d k 2c 1e 2b
Fast
i 1a 1f 1g 1c 1d l 1b
Middle
j n
Slow
h 2a 2f 2g 2e 2d 2c 1e 2b
Start
i 1a 1f 1g 1c 1d l 1b
End
j n
r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 100 150 200
Kcal
o p
o p
gC
m
m
k
Temp
323
Defrost
Open
Preheat
Keep Warm
Timer
CHAPTER 15
VFD CONTROLLER/DRIVER
The light timing of each segment is discussed next. In display example (3) in 15.9, a segment spans two grids (that is, 2G and 3G, 4G and 5G). Therefore, these segments will be lit at the timing from T0 to T6 as shown in Figure 15-20. For example, when "Fast" is to be lit as shown in example (3) in 15.9, the lighting timing must be T5 in Figure 15-20 because the "Fast" segment spans the 4G and 5G grids. In addition, it can be seen from Figure 15-3 that the "Fast" segment, that is, "i" segment which spans 4G and 5G, can be lit in the T5 cycle. Figure 15-20. Grid Driving Timing
5G
4G
3G
2G 1 display cycle 1G T0 T1 T2 T3 T4 T5 T6 T0
Key scan timing
Table 15-3. Segment Lighting Timing
Lighting Segment T0 T1 T2 T3 T4 T5 T6 q, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13 1b, 1c, j, m, n, o, p 1a, 1g, 1d, i, l 2a, 2b, 2c, 2d, 2e, 2f, 2g, h, k, 1e, 1f 1b, 1c, j, m, n, o, p 1a, 1g, 1d, i, l 2a, 2b, 2c, 2d, 2e, 2f, 2g, h, k, 1e, 1f
324
User's Manual U11302EJ4V0UM
Figure 15-21. Data Memory Status in 23-Segment x 5-Grid Display Mode
FA7x 0 0 0 0 0 1 0
User's Manual U11302EJ4V0UM
FA6x 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0
FA5x 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0
FA4x 1 0 0 0 0 0 0 T0 T1 T2 T3 T4 T5
CHAPTER 15
0 0 0 0 0 0 0
1 0 0 0 0 0 1
0 0 0 0 1 0 0
0 0 0 0 0 0 0
T6
S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
VFD CONTROLLER/DRIVER
FIP27 FIP26 FIP25 FIP24 FIP23 FIP22 FIP21 FIP20 FIP19 FIP18 FIP17 FIP16 FIP15 FIP14 FIP13 FIP12 FIP11 FIP10 FIP9 FIP8 FIP7 FIP6 FIP5 FIP4 FIP3 FIP2 FIP1 FIP0
P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 G5 G4 G3 G2 G1
Heating
h
2a 2f 2g 2e 2d 2c 1e 2b
Fast
i
1a 1f 1g 1c 1d 1b
Middle
j
n
Slow
h
2a 2f 2g 2e 2d 2c 2b
Start
i
1a 1f 1g 1e 1d 1c 1b
End
n j
r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13
300 q 250
Kcal
o p
o p
200
gC
m
150
k
l
m
k
l
Temp
5G
Defrost
Open
4G
Preheat
3G
Keep Warm
Timer
2G
100
1G
325
CHAPTER 15
VFD CONTROLLER/DRIVER
15.10 Calculating Total Power Dissipation
The total power dissipation of the PD780208 Subseries is the sum of the values of the following three parts. Design your application set so that the sum is lower than the total power dissipation PT stipulated in Figure 15-22. (The recommended operating condition is 80% or lower of the rated value.) <1> CPU: The power consumed by the CPU and calculated with VDD (max.) x IDD (max.) <2> Output pins: The power dissipation when the maximum current flows through the display output pins <3> Pull-down resistors: The power consumed at the on-chip pull-down resistors connected to the display output pins Figure 15-22. Allowable Total Power Dissipation PT (TA = -40 to +85C)
Power dissipation PT [mW]
800 600 400 200
-40
0
+40 Temperature [C ]
+80
The following example assumes the case where the display examples shown in 15.9 are displayed. 15.10.1 Segment type (display mode 1: DSPM05 = 0) The calculation method for the total power dissipation in the case of the display example in Figure 15-23 is described below. Example Assume the following conditions: VDD = 5 V 10%, 5.0 MHz oscillation Supply current (IDD) = 21.6 mA Display output: 11 grids x 10 segments (cut width = 1/16: when DIMS1 to DIMS3 = 000B) Maximum current at the grid pin is 15 mA. Maximum current at the segment pin is 3 mA. At the key scan timing, display output pin is OFF. Display output voltage: grid VOD = VDD - 2 V (voltage drop of 2 V) segments VOD = VDD - 0.4 V (voltage drop of 0.4 V) Fluorescent display control voltage (VLOAD) = -35 V Mask option pull-down resistor = 25 k
326
User's Manual U11302EJ4V0UM
CHAPTER 15
VFD CONTROLLER/DRIVER
By placing the above conditions in calculations <1> to <3>, the total dissipation can be worked out. <1> CPU power dissipation: 5.5 V x 21.6 mA = 118.8 mW <2> Output pin power dissipation: Total current value of each grid No. of grids + 1 15 mA x 11 grids 11 grids + 1 x (1 - 1 16 x Digit width (1 - Cut width) = = 2.9 mW )
Grid
(VDD - VOD) x 2Vx
x Digit width (1 - Cut width) = = 25.8 mW
Segment (VDD - VOD) x
Total segment current value of illuminated dots No. of grids + 1 3 mA x 31 dots 11 grids + 1 x (1 - 1 16 )
0.4 V x
<3> Pull-down resistor power dissipation: (VOD - VLOAD)2 Pull-down resistor value (5.5 V - 2 V - (-35 V))2 25 k Segment (VOD - VLOAD)2 Pull-down resistor value 25 k No. of grids No. of grids + 1 11 grids 11 grids + 1
Grid
x x x
x Digit width (1 - Cut width) = 1 16 x Digit width (1 - Cut width) = ) = 155.8 mW ) = 50.9 mW
x (1 -
No. of illuminated dots No. of grids + 1 x 31 dots 11 grids + 1 x (1 - 1
(5.5 V - 0.4 V - (-35 V))2
16
Total power dissipation = <1> + <2> + <3> = 118.8 + 25.8 + 2.9 + 50.9 + 155.8 = 354.2 mW In this example, the power dissipation problem is cleared because the total power dissipation does not exceed the allowable total power dissipation rating shown in Figure 15-22.
User's Manual U11302EJ4V0UM
327
CHAPTER 15
VFD CONTROLLER/DRIVER
Figure 15-23 shows a display example and display data for "segment type". Figure 15-23. Relationship Between Display Data Memory Contents and Segment Outputs in 10-Segment x 11-Digit Display Mode
Display data memory
FA7AH FA79H FA78H FA77H FA76H FA75H FA74H FA73H FA72H FA71H FA70H FA6AH FA69H FA68H FA67H FA66H FA65H FA64H FA63H FA62H FA61H FA60H 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 1 0 0 0 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 1 0 1 1 1 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 FA7xH Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 FA6xH Bit 6
S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 a b c d e f g h i j
T10
T9
T8
T7
T6
T5
T4
T3
T2
T1
T0
i AM i PM j 0
SUN
MON
TUE j j
WED
THU
FRI
SAT f
a gb edc 10 h
1
2
3
4
5
6
7
8
9
328
User's Manual U11302EJ4V0UM
CHAPTER 15
VFD CONTROLLER/DRIVER
15.10.2 Dot type (display mode 1: DSPM05 = 0) The calculation method for the total power dissipation in the case of the display example in Figure 15-24 is described below. Example Assume the following conditions: VDD = 5 V 10%, 5.0 MHz oscillation Supply current (IDD) = 21.6 mA Display output: 16 grids x 35 segments (cut width = 1/16: when DIMS1 to DIMS3 = 000B) Maximum current at the grid pin is 15 mA. Maximum current at the segment pin is 3 mA. At the key scan timing, display output pin is OFF. Display output voltage: grid VOD = VDD - 2 V (voltage drop of 2 V) segments VOD = VDD - 0.4 V (voltage drop of 0.4 V) Fluorescent display control voltage (VLOAD) = -35 V Mask option pull-down resistor = 25 k By placing the above conditions in calculation <1> to <3>, the total dissipation can be worked out. <1> CPU power dissipation: 5.5 V x 21.6 mA = 118.8 mW <2> Output pin power dissipation: Total current value of each grid No. of grids + 1 15 mA x 16 grids 16 grids + 1 x (1 - 1 16 x Digit width (1 - Cut width) = = 11.1 mW )
Grid
(VDD - VOD) x 2Vx
x Digit width (1 - Cut width) = = 26.5 mW
Segment (VDD - VOD) x
Total segment current value of illuminated dots No. of grids + 1 3 mA x 168 dots 16 grids + 1 x (1 - 1 16 )
0.4 V x
<3> Pull-down resistor power dissipation: (VOD - VLOAD)2 Pull-down resistor value (5.5 V - 2 V - (-35 V))2 25 k Segment (VOD - VLOAD)2 Pull-down resistor value 25 k No. of grids No. of grids + 1 16 grids 16 grids + 1
Grid
x x x
x Digit width (1 - Cut width) = 1 16 x Digit width (1 - Cut width) = ) = 595.9 mW ) = 52.3 mW
x (1 -
No. of illuminated dots No. of grids + 1 x 168 dots 16 grids + 1 x (1 - 1
(5.5 V - 0.4 V - (-35 V))2
16
Total power dissipation = <1> + <2> + <3> = 118.8 + 26.5 + 11.1 + 52.3 + 595.9 = 804.6 mW In this example, the total power dissipation exceeds the allowable total power dissipation rating shown in Figure 15-22. In this case, the power dissipation can be lowered by reducing the number of enabled on-chip pull-down resistors. Next, calculation expressions are shown for the display example where on-chip pull-down resistors are enabled for S0 through S24 only.
User's Manual U11302EJ4V0UM
329
CHAPTER 15
VFD CONTROLLER/DRIVER
<3> Pull-down resistor power dissipation: (VOD - VLOAD)2 Pull-down resistor value (5.5 V - 2 V - (-35 V))2 25 k Segment (VOD - VLOAD)2 Pull-down resistor value 25 k No. of grids No. of grids + 1 16 grids 16 grids + 1
Grid
x x x
x Digit width (1 - Cut width) = 1 16 x Digit width (1 - Cut width) = ) = 390.2 mW ) = 52.3 mW
x (1 -
No. of illuminated dots No. of grids + 1 x 110 dots 16 grids + 1 x (1 - 1
(5.5 V - 0.4 V - (-35 V))2
16
Total power dissipation = <1> + <2> + <3> = 118.8 + 26.5 + 11.1 + 52.3 + 390.2 = 598.9 mW In this manner, design the system so that the power dissipation does not exceed the allowable total power dissipation rating. Figure 15-24 shows a display example and display data for "dot type".
330
User's Manual U11302EJ4V0UM
CHAPTER 15
VFD CONTROLLER/DRIVER
Figure 15-24. Relationship Between Display Data Memory Contents and Segment Outputs in 35-Segment x 16-Digit Display Mode
Display data memory
FA7FH FA7EH FA7DH FA7CH FA7BH FA7AH FA79H FA78H FA77H FA76H FA75H FA74H FA73H FA72H FA71H FA70H FA6FH FA6EH FA6DH FA6CH FA6BH FA6AH FA69H FA68H FA67H FA66H FA65H FA64H FA63H FA62H FA61H FA60H FA5FH FA5EH FA5DH FA5CH FA5BH FA5AH FA59H FA58H FA57H FA56H FA55H FA54H FA53H FA52H FA51H FA50H FA4FH FA4EH FA4DH FA4CH FA4BH FA4AH FA49H FA48H FA47H FA46H FA45H FA44H FA43H FA42H FA41H FA40H FA3FH FA3EH FA3DH FA3CH FA3BH FA3AH FA39H FA38H FA37H FA36H FA35H FA34H FA33H FA32H FA31H FA30H S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S18 S17 S0 to S34 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 1 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 1 0 1 1 1 1 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 0 1 1 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 1 1 0 0 1 1 1 0 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 0 Bit 7 6 5 FA3xH FA4xH FA5xH FA6xH FA7xH
T15 T14 T13 T12 T11 T10
T9
T8
T7
T6
T5
T4
T3
T2
T1
T0
User's Manual U11302EJ4V0UM
331
CHAPTER 15
VFD CONTROLLER/DRIVER
15.10.3 Display type in which a segment spans two or more grids (display mode 2: DSPM05 = 1) The calculation method for the total power dissipation in the case of the display example in Figure 15-26 is described below. Example Assume the following conditions: VDD = 5 V 10%, 5.0 MHz oscillation Supply current (IDD) = 21.6 mA Display output: 23 segments x 7 patterns (cut width = 1/16: when DIMS1 to DIMS3 = 000B) Maximum current at the display output pin is 15 mA. Display output voltage (VOD) = VDD - 2 V (voltage drop of 2 V) Fluorescent display control voltage (VLOAD) = -35 V Mask option pull-down resistor = 25 k By placing the above conditions in calculation <1> to <3>, the total dissipation can be worked out. <1> CPU power dissipation: 5.5 V x 21.6 mA = 118.8 mW <2> Output pin power dissipation: Total current value of each grid No. of grids + 1 15 mA x 9 grids 7 grids + 1 x (1 - 1 16 )
(VDD - VOD) x 2Vx
x Digit width (1 - Cut width) = = 31.6 mW
<3> Pull-down resistor power dissipation: (VOD - VLOAD)2 Pull-down resistor value (5.5 V - 2 V - (-35 V))2 25 k Segment (VOD - VLOAD)2 Pull-down resistor value 25 k No. of grids No. of grids + 1 9 grids 7 grids + 1
Grid
x x x
x Digit width (1 - Cut width) = 1 16 x Digit width (1 - Cut width) = ) = 152.8 mW ) = 62.5 mW
x (1 -
No. of illuminated dots No. of grids + 1 x 22 dots 7 grids + 1 x (1 - 1
(5.5 V - 0.5 V - (-35 V))2
16
Total power dissipation = <1> + <2> + <3> = 118.8 + 31.6 + 62.5 + 152.8 = 365.7 mW In this example, the power dissipation problem is cleared because the total power dissipation does not exceed the allowable total power dissipation rating shown in Figure 15-22. Figure 15-25 shows the grid driving timing, and Figure 15-26 shows a display example and display data of a display type in which a segment spans two or more grids.
332
User's Manual U11302EJ4V0UM
CHAPTER 15
VFD CONTROLLER/DRIVER
Figure 15-25. Grid Driving Timing
5G
4G
3G
2G 1 display cycle 1G T0 T1 T2 T3 T4 T5 T6 T0
Key scan timing
User's Manual U11302EJ4V0UM
333
334
FA7x 0 0 0 0 0 1 0
User's Manual U11302EJ4V0UM
Figure 15-26. Data Memory Status in 23-Segment x 5-Grid Display Mode
FA6x 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0
FA5x 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0
FA4x 1 0 0 0 0 0 0 T0 T1 T2 T3 T4 T5
CHAPTER 15
0 0 0 0 0 0 0
1 0 0 0 0 0 1
0 0 0 0 1 0 0
0 0 0 0 0 0 0
T6
S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
VFD CONTROLLER/DRIVER
FIP27 FIP26 FIP25 FIP24 FIP23 FIP22 FIP21 FIP20 FIP19 FIP18 FIP17 FIP16 FIP15 FIP14 FIP13 FIP12 FIP11 FIP10 FIP9 FIP8 FIP7 FIP6 FIP5 FIP4 FIP3 FIP2 FIP1 FIP0
P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 G5 G4 G3 G2 G1
Heating
h
2a 2f 2g 2e 2d 2c 1e 2b
Fast
i
1a 1f 1g 1c 1d 1b
Middle
j
n
Slow
h
2a 2f 2g 2e 2d 2c 2b
Start
i
1a 1f 1g 1e 1d 1c 1b
End
n j
r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13
300 q 250
Kcal
o p
o p
200
gC
m
150
k
l
m
k
l
Temp
5G
Defrost
Open
4G
Preheat
3G
Keep Warm
Timer
2G
100
1G
CHAPTER 16 INTERRUPT AND TEST FUNCTIONS
16.1 Interrupt Function Types
The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally (that is, even in the interrupt disabled state). It does not undergo interrupt priority control and is given top priority over all other interrupt requests. A standby release signal is generated. One interrupt request from the watchdog timer is provided as a non-maskable interrupt. (2) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag register (PR0L and PR0H). Multiple interrupt servicing of high-priority interrupts can be applied to low-priority interrupts. If two or more interrupts with the same priority are simultaneously generated, each interrupt has a predetermined priority (see Table 16-1). A standby release signal is generated. Four external interrupt requests and 9 internal interrupt requests are provided as maskable interrupts. (3) Software interrupt This is a vectored interrupt generated by executing the BRK instruction. It is acknowledged even in the interrupt disabled state. The software interrupt does not undergo interrupt priority control.
User's Manual U11302EJ4V0UM
335
CHAPTER 16
INTERRUPT AND TEST FUNCTIONS
16.2 Interrupt Sources and Configuration
A total of 15 interrupt sources are provided including non-maskable, maskable, and software interrupts (see Table 16-1). Table 16-1. Interrupt Source List
Interrupt Type Default PriorityNote 1 Name INTWDT Interrupt Source Trigger Watchdog timer overflow (with watchdog timer mode 1 selected) Watchdog timer overflow (with interval timer mode selected) Pin input edge detection External 0006H 0008H 000AH 000CH End of serial interface channel 0 transfer End of serial interface channel 1 transfer Reference time interval signal from watch timer Generation of 16-bit timer/event counter match signal Generation of 8-bit timer/event counter 1 match signal Generation of 8 bit timer/event counter 2 match signal End of A/D converter conversion Key scan timing from VFD controller/driver BRK instruction execution -- Internal 000EH 0010H 0012H (B) Internal/ External Vector Table Address 0004H Basic Configuration TypeNote 2 (A)
Nonmaskable Maskable
--
Internal
0
INTWDT
(B)
1 2 3 4 5 6 7
INTP0 INTP1 INTP2 INTP3 INTCSI0 INTCSI1 INTTM3
(C) (D)
8
INTTM0
0014H
9
INTTM1
0016H
10
INTTM2
0018H
11 12 Software --
INTAD INTKS BRK
001AH 001CH 003EH (E)
Notes 1. Default priorities are intended for two or more simultaneously generated maskable interrupt requests. 0 is the highest priority and 12 is the lowest priority. 2. Basic configuration types (A) through (E) correspond to (A) through (E) on the following pages.
336
User's Manual U11302EJ4V0UM
CHAPTER 16
INTERRUPT AND TEST FUNCTIONS
Figure 16-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt
Internal bus
Interrupt request
Priority controller
Vector table address generator Standby release signal
(B) Internal maskable interrupt
Internal bus
MK
IE
PR
ISP
Interrupt request
IF
Priority controller
Vector table address generator Standby release signal
(C) External maskable interrupt (INTP0)
Internal bus
Sampling clock select register (SCS)
External interrupt mode register (INTM0)
MK
IE
PR
ISP
Interrupt request
Sampling clock
Edge detector
IF
Priority controller
Vector table address generator Standby release signal
User's Manual U11302EJ4V0UM
337
CHAPTER 16
INTERRUPT AND TEST FUNCTIONS
Figure 16-1. Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupt (except INTP0)
Internal bus
External interrupt mode register (INTM0)
MK
IE
PR
ISP
Interrupt request
Edge detector
IF
Priority controller
Vector table address generator
Standby release signal
(E) Software interrupt
Internal bus
Interrupt request
Vector table address generator
IF: IE:
Interrupt request flag Interrupt enable flag
ISP: In-service priority flag MK: Interrupt mask flag PR: Priority specification flag
338
User's Manual U11302EJ4V0UM
CHAPTER 16
INTERRUPT AND TEST FUNCTIONS
16.3 Interrupt Function Control Registers
The following six types of registers are used to control the interrupt functions. * Interrupt request flag register (IF0L, IF0H) * Interrupt mask flag register (MK0L, MK0H) * Priority specification flag register (PR0L, PR0H) * External interrupt mode register (INTM0) * Sampling clock select register (SCS) * Program status word (PSW) Table 16-2 gives a listing of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources. Table 16-2. Various Flags Corresponding to Interrupt Request Sources
Interrupt Source Interrupt Request Flag Register INTWDT INTP0 INTP1 INTP2 INTP3 INTCSI0 INTCSI1 INTTM3 INTTM0 INTTM1 INTTM2 INTAD INTKS TMIF4 PIF0 PIF1 PIF2 PIF3 CSIIF0 CSIIF1 TMIF3 TMIF0 TMIF1 TMIF2 ADIF KSIF IF0H IF0L TMMK4 PMK0 PMK1 PMK2 PMK3 CSIMK0 CSIMK1 TMMK3 TMMK0 TMMK1 TMMK2 ADMK KSMK MK0H Interrupt Mask Flag Register MK0L TMPR4 PPR0 PPR1 PPR2 PPR3 CSIPR0 CSIPR1 TMPR3 TMPR0 TMPR1 TMPR2 ADPR KSPR PR0H Priority Specification Flag Register PR0L
User's Manual U11302EJ4V0UM
339
CHAPTER 16
INTERRUPT AND TEST FUNCTIONS
(1) Interrupt request flag registers (IF0L, IF0H) The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET. IF0L and IF0H are set with a 1-bit or 8-bit memory manipulation instruction. If IF0L and IF0H are used as a 16-bit register IF0, use a 16-bit memory manipulation instruction for setting. RESET input clears these registers to 00H. Figure 16-2. Format of Interrupt Request Flag Register
Symbol <7> <6> <5> <4> PIF3 <3> PIF2 <2> PIF1 <1> PIF0 <0> TMIF4 Address FFE0H After reset 00H R/W R/W
IF0L TMIF3 CSIIF1 CSIIF0
7 IF0H 0
6 0
<5> WTIF
Note
<4> KSIF
<3> ADIF
<2>
<1>
<0> FFE1H 00H R/W
TMIF2 TMIF1 TMIF0
xxIF 0 1
Interrupt request flag No interrupt request signal
Interrupt request signal is generated: Interrupt request state
Note
WTIF is the test input flag. A vectored interrupt request is not generated.
Cautions 1. The TMIF4 flag is R/W enabled only when the watchdog timer is used as an interval timer. If the watchdog timer is used in watchdog timer mode 1, set the TMIF4 flag to 0. 2. Always set bits 6 and 7 of IF0H to 0. 3. When an interrupt is acknowledged, the interrupt request flag is automatically cleared, and then servicing of the interrupt routine is started. 4. When the interrupt request flag register is manipulated (including by a 1-bit memory manipulation instruction), if an interrupt request corresponding to another flag in the same register is generated, the flag corresponding to that interrupt request may not be set to 1.
340
User's Manual U11302EJ4V0UM
CHAPTER 16
INTERRUPT AND TEST FUNCTIONS
(2) Interrupt mask flag registers (MK0L, MK0H) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt servicing and to set standby clear enable/disable. MK0L and MK0H are set with a 1-bit or 8-bit memory manipulation instruction. If MK0L and MK0H are used as a 16-bit register MK0, use a 16-bit memory manipulation instruction for setting. RESET input sets these registers to FFH. Figure 16-3. Format of Interrupt Mask Flag Register
Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address FFE4H After reset FFH R/W R/W
MK0L TMMK3 CSIMK1 CSIMK0 PMK3 PMK2 PMK1 PMK0 TMMK4
7 MK0H 1
6 1
<5> WTMK
Note
<4>
<3>
<2>
<1>
<0> FFE5H FFH R/W
KSMK ADMK TMMK2 TMMK1 TMMK0
xxMK 0 1
Interrupt servicing and standby mode control
Interrupt servicing enabled, standby mode release enabled Interrupt servicing disabled, standby mode release disabled
Note
WTMK controls standby mode release enable/disable. This bit does not control the interrupt function.
Cautions 1. If the TMMK4 flag is read when the watchdog timer is used in watchdog timer mode 1, the MK0 value becomes undefined. 2. Because port 0 has an alternate function as an external interrupt request input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output mode. 3. Always set bits 6 and 7 of MK0H to 1.
User's Manual U11302EJ4V0UM
341
CHAPTER 16
INTERRUPT AND TEST FUNCTIONS
(3) Priority specification flag registers (PR0L, PR0H) The priority specification flag is used to set the corresponding maskable interrupt priority order. PR0L and PR0H are set with a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are used as a 16-bit register PR0, use a 16-bit memory manipulation instruction for setting. RESET input sets these registers to FFH. Figure 16-4. Format of Priority Specification Flag Register
Symbol <7> <6> <5> <4> <3> PPR2 <2> PPR1 <1> <0> Address FFE8H After reset FFH R/W R/W
PR0L TMPR3 CSIPR1 CSIPR0 PPR3
PPR0 TMPR4
7 PR0H 1
6 1
5 1
<4>
<3>
<2>
<1>
<0> FFE9H FFH R/W
KSPR ADPR TMPR2 TMPR1 TMPR0
xxPR 0 1
Priority level selection High priority level Low priority level
Cautions 1. When the watchdog timer is used in watchdog timer mode 1, set the TMPR4 flag to 1. 2. Always set bits 5 to 7 of PR0H to 1.
342
User's Manual U11302EJ4V0UM
CHAPTER 16
INTERRUPT AND TEST FUNCTIONS
(4) External interrupt mode register (INTM0) This register sets the valid edge for INTP0 to INTP2 and TI0. INTM0 is set with an 8-bit memory manipulation instruction. RESET input clears INTM0 to 00H. Remarks 1. INTP0 is also used for TI0/P00. 2. INTP3 is fixed to the falling edge. Figure 16-5. Format of External Interrupt Mode Register
Symbol INTM0 7 6 5 4 3 2 1 0 0 0 Address FFECH After reset 00H R/W R/W
ES31 ES30 ES21 ES20 ES11 ES10
ES11 0 0 1 1
ES10 0 1 0 1
INTP0/TI0 valid edge selection Falling edge Rising edge Setting prohibited Both falling and rising edges
ES21 0 0 1 1
ES20 0 1 0 1
INTP1 valid edge selection Falling edge Rising edge Setting prohibited Both falling and rising edges
ES31 0 0 1 1
ES30 0 1 0 1
INTP2 valid edge selection Falling edge Rising edge Setting prohibited Both falling and rising edges
Caution When using the INTP0/TI0/P00 pin as a timer input pin (TI0), stop the operation of the 16-bit timer by clearing bits 1 to 3 (TMC01 to TMC03) of the 16-bit timer mode control register (TMC0) to 0, 0, 0, before setting the valid edge of TI0. When using the INTP0/TI0/P00 pin as an external interrupt input pin (INTP0), the valid edge of INTP0 may be set while the 16-bit timer is operating.
User's Manual U11302EJ4V0UM
343
CHAPTER 16
INTERRUPT AND TEST FUNCTIONS
(5) Sampling clock select register (SCS) This register is used to set the clock used to sample the valid edge input to INTP0. When remote controlled data reception is carried out using INTP0, digital noise is eliminated using the sampling clock. SCS is set with an 8-bit memory manipulation instruction. RESET input clears SCS to 00H. Figure 16-6. Format of Sampling Clock Select Register
Symbol SCS 7 0 6 0 5 0 4 0 3 0 2 0 1 0 Address FF47H After reset 00H R/W R/W
SCS1 SCS0
SCS1 SCS0 0 0 1 1 0 1 0 1
INTP0 sampling clock selection fX/2N + 1 Setting prohibited fX/26 (78.1 kHz) fX/27 (39.1 kHz)
Caution fX/2N + 1 is the clock supplied to the CPU, fX/26 and fX/27 are the clocks supplied to the peripheral hardware. fX/2N + 1 stops in the HALT mode. Remarks 1. N: Value (N = 0 to 4) of bits 0 to 2 (PCC0 to PCC2) of processor clock control register (PCC) 2. fX: Main system clock oscillation frequency 3. Figures in parentheses apply to operation with fX = 5.0 MHz.
344
User's Manual U11302EJ4V0UM
CHAPTER 16
INTERRUPT AND TEST FUNCTIONS
The noise eliminator sets the interrupt request flag (PIF0) to 1 if the input level of the sampled INTP0 is active twice in succession. Figure 16-7 shows the noise eliminator I/O timing. Figure 16-7. Noise Eliminator I/O Timing (When Rising Edge Is Detected) (a) When input is less than the sampling cycle (tSMP)
tSMP Sampling clock
INTP0
PIF0
"L" The PIF0 output remains low because the level of INTP0 is not high when it is sampled.
(b) When input is equal to or twice the sampling cycle (tSMP)
tSMP Sampling clock
INTP0
<1>
<2>
PIF0 The PIF0 flag is set to 1 because the sampled INTP0 level is high twice in succession in <2>.
(c) When input is twice or more than the sampling cycle (tSMP)
tSMP Sampling clock
INTP0
PIF0 The PIF0 flag is set to 1 when INTP0 goes high twice in succession.
User's Manual U11302EJ4V0UM
345
CHAPTER 16
INTERRUPT AND TEST FUNCTIONS
(6) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for interrupt requests. The IE flag used to set maskable interrupt enable/disable and the ISP flag used to control multiple interrupt servicing are mapped to the PSW. Besides 8-bit unit read/write, this register can carry out operations using bit manipulation and dedicated instructions (EI and DI). When a vectored interrupt request is acknowledged or when the BRK instruction is executed, the contents of the PSW are automatically saved into the stack, and the IE flag is reset to 0. If a maskable interrupt request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are transferred to the ISP flag. The contents of the PSW are also saved to the stack by the PUSH PSW instruction. They are reset from the stack with the RETI, RETB, and POP PSW instructions. RESET input sets PSW to 02H. Figure 16-8. Format of Program Status Word
Symbol PSW 7 IE 6 Z 5 RBS1 4 AC 3 RBS0 2 0 1 ISP 0 CY
After reset 02H Used when normal instruction is executed ISP 0 Priority of interrupt currently being serviced High-priority interrupt servicing (low-priority interrupts disabled) Interrupt request not acknowledged or low-priority interrupt servicing (all maskable interrupts enabled)
1
IE 0 1
Interrupt request acknowledgment enable/disable Disabled Enabled
346
User's Manual U11302EJ4V0UM
CHAPTER 16
INTERRUPT AND TEST FUNCTIONS
16.4 Interrupt Servicing Operations
16.4.1 Non-maskable interrupt request acknowledgment operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledgment disabled state. It does not undergo interrupt priority control and has highest priority over all other interrupts. If a non-maskable interrupt request is acknowledged, the contents of program status word (PSW) and program counter (PC) are saved in the stacks in that order. Then, the IE and ISP flags are reset to 0, and the vector table contents are loaded into the PC and branched. A new non-maskable interrupt request generated during execution of a non-maskable interrupt servicing program is acknowledged after execution of the current non-maskable interrupt servicing program is terminated (following RETI instruction execution) and one main routine instruction is executed. If a new non-maskable interrupt request is generated twice or more during non-maskable interrupt service program execution, only one non-maskable interrupt request is acknowledged after termination of the non-maskable interrupt service program execution. Figure 16-9 shows the flowchart illustrating generation and acknowledgment of a non-maskable interrupt request. Figure 16-10 shows the timing of acknowledging a non-maskable interrupt request. Figure 16-11 illustrates how nested non-maskable interrupt requests are acknowledged.
User's Manual U11302EJ4V0UM
347
CHAPTER 16
INTERRUPT AND TEST FUNCTIONS
Figure 16-9. Non-Maskable Interrupt Request Acknowledgment Flowchart
Start
WDTM4 = 1 (with watchdog timer mode selected)? Yes
No Interval timer
Overflow in WDT?
No
Yes WDTM3 = 0 (with non-maskable interrupt request selected)? Yes Interrupt request generation No Reset processing
WDT interrupt servicing?
No Interrupt request held pending
Yes
Interrupt control register unaccessed?
No
Yes Interrupt service start
WDTM: Watchdog timer mode register WDT: Watchdog timer
Figure 16-10. Non-Maskable Interrupt Request Acknowledgment Timing
CPU processing
Instruction
Instruction
PSW and PC save, jump to interrupt servicing
Interrupt servicing program
TMIF4
Interrupt request generated during this interval is acknowledged at
.
TMIF4: Watchdog timer interrupt request flag
348
User's Manual U11302EJ4V0UM
CHAPTER 16
INTERRUPT AND TEST FUNCTIONS
Figure 16-11. Non-Maskable Interrupt Request Acknowledgment Operation (a) If a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution
Main routine
NMI request <1> NMI request <2> Execution of 1 instruction
Execution of NMI request <1> NMI request <2> held pending
Servicing of pending NMI request <2>
(b)
If two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution
Main routine
NMI request <1> NMI request <2> Execution of 1 instruction NMI request <3>
Execution of NMI request <1> NMI request <2> held pending NMI request <3> held pending
Servicing of pending NMI request <2>
NMI request <3> not acknowledged (Although two or more NMI requests have been generated, only one request is acknowledged.)
User's Manual U11302EJ4V0UM
349
CHAPTER 16
INTERRUPT AND TEST FUNCTIONS
16.4.2 Maskable interrupt request acknowledgment operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the mask (MK) flag of the interrupt request is cleared to 0. A vectored interrupt request is acknowledged in the interrupt enabled state (with IE flag set to 1). However, a low-priority interrupt is not acknowledged during high-priority interrupt request servicing (with ISP flag reset to 0). Table 16-3 shows the time required until interrupt servicing is executed after a maskable interrupt request has been generated. For the interrupt request acknowledgment timing, refer to Figures 16-13 and 16-14. Table 16-3. Times from Maskable Interrupt Request Generation to Interrupt Servicing
Minimum Time When xxPR = 0 When xxPR = 1 7 clock cycles 8 clock cycles Maximum TimeNote 32 clock cycles 33 clock cycles
Note
If an interrupt request is generated just before a divide instruction, the wait time is maximized.
Remark 1 clock cycle = 1/fCPU (fCPU: CPU clock) If two or more maskable interrupt requests are generated simultaneously, the request specified as higher priority by the priority specification flag is acknowledged first. If the same priority is specified by the priority specification flag, the interrupt with the highest default priority is acknowledged first. Any pending interrupt requests are acknowledged when they become acknowledgeable. Figure 16-12 shows interrupt request acknowledgment algorithms. If a maskable interrupt request is acknowledged, the contents of the program status word (PSW) and program counter (PC) are saved in the stacks in that order. Then, the IE flag is reset to 0, and the acknowledged interrupt request priority specification flag contents are transferred to the ISP flag. Further, the vector table data determined for each interrupt request is loaded into the PC and branched. Return from the interrupt is possible with the RETI instruction.
350
User's Manual U11302EJ4V0UM
CHAPTER 16
INTERRUPT AND TEST FUNCTIONS
Figure 16-12. Interrupt Request Acknowledge Processing Algorithm
Start
No
xxIF = 1?
Yes (interrupt request generation)
No
xxMK = 0?
Yes
Interrupt request held pending
Yes (high priority)
xxPR = 0?
No (low priority)
Yes
Interrupt request held pending
Any highpriority interrupt request among simultaneously generated xxPR = 0 interrupt requests? No No
Any simultaneously generated xx PR = 0 interrupt requests? No Any simultaneously generated high-priority interrupt requests? No
Yes Interrupt request held pending
IE = 1?
Yes Vectored interrupt servicing
Yes Interrupt request held pending No Interrupt request held pending No Interrupt request held pending
Interrupt request held pending
IE = 1?
Yes
ISP = 1?
Yes Vectored interrupt servicing
xxIF:
Interrupt request flag
xxMK: Interrupt mask flag xxPR: Priority specification flag IE: ISP: Flag controlling acknowledgment of maskable interrupt request (1 = Enabled, 0 = Disabled) Flag indicating priority of interrupt currently serviced (0 = Interrupt with high priority is serviced, 1 = No interrupt request is acknowledged, or interrupt with low priority is serviced)
User's Manual U11302EJ4V0UM
351
CHAPTER 16
INTERRUPT AND TEST FUNCTIONS
Figure 16-13. Interrupt Request Acknowledgment Timing (Minimum Time)
6 clocks
PSW and PC save, jump to interrupt servicing Interrupt servicing program
CPU processing
Instruction
Instruction
xxIF (xxPR = 1) 8 clocks xxIF (xx PR = 0) 7 clocks
Remark 1 clock cycle = 1/fCPU (fCPU: CPU clock) Figure 16-14. Interrupt Request Acknowledgment Timing (Maximum Time)
25 clocks 6 clocks
PSW and PC save, jump to interrupt servicing Interrupt servicing program
CPU processing
Instruction
Divide instruction
xxIF (xx PR = 1) 33 clocks xxIF (xx PR = 0) 32 clocks
Remark 1 clock cycle = 1/fCPU (fCPU: CPU clock) 16.4.3 Software interrupt request acknowledgment operation A software interrupt request is acknowledged by BRK instruction execution. Software interrupts cannot be disabled. If a software interrupt request is acknowledged, the contents of the program status word (PSW) and program counter (PC) are saved in the stacks in that order, the IE flag is reset to 0 and the contents of the vector tables (003EH and 003FH) are loaded into the PC and branched. Return from the software interrupt is possible with the RETB instruction. Caution Do not use the RETI instruction for returning from the software interrupt.
352
User's Manual U11302EJ4V0UM
CHAPTER 16
INTERRUPT AND TEST FUNCTIONS
16.4.4 Multiple interrupt servicing Multiple interrupt servicing occurs when an interrupt request is acknowledged during execution of another interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected (IE = 1) (except non-maskable interrupts). Also, when an interrupt request is received, interrupt request acknowledgment becomes disabled (IE = 0). Therefore, to enable multiple interrupt servicing, it is necessary to set (to 1) the IE flag with the EI instruction during interrupt servicing to enable interrupt acknowledgment. Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to interrupt priority control. Two types of priority control are available: default priority control and programmable priority control. Programmable priority control is used for multiple interrupt servicing. In the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt servicing. Interrupt requests that are not enabled because the interrupt disabled state is set or they have a lower priority are held pending. When servicing of the current interrupt ends, the pending interrupt request is acknowledged following execution of one main processing instruction. Multiple interrupt servicing is not possible during non-maskable interrupt servicing. Table 16-4 shows interrupt requests enabled for multiple interrupt servicing, and Figure 16-15 shows multiple interrupt servicing examples. Table 16-4. Interrupt Request Enabled for Multiple Interrupt During Interrupt Servicing
Multiple Interrupt Non-Maskable Servicing Request Interrupt Request Interrupt Servicing Non-maskable interrupt Maskable interrupt ISP = 0 ISP = 1 Software interrupt D E E E Maskable Interrupt Request xxPR = 0 IE = 1 D E E E IE = 0 D D D D xxPR = 1 IE = 1 D D E E IE = 0 D D D D E E E E Software Interrupt Request
Remarks 1. E: Multiple interrupt servicing enabled D: Multiple interrupt servicing disabled 2. ISP and IE are flags contained in the PSW. ISP = 0: An interrupt with higher priority is being serviced ISP = 1: An interrupt request is not acknowledged or an interrupt with lower priority is being serviced IE = 0: IE = 1: Interrupt request acknowledgment is disabled Interrupt request acknowledgment is enabled
3. xxPR is a flag contained in PR0L and PR0H. xxPR = 0: Higher priority level xxPR = 1: Lower priority level
User's Manual U11302EJ4V0UM
353
CHAPTER 16
INTERRUPT AND TEST FUNCTIONS
Figure 16-15. Multiple Interrupt Servicing Example (1/2) Example 1. Two interrupts are generated
Main processing INTxx servicing IE = 0 EI EI INTyy (PR = 0) INTzz (PR = 0) RETI RETI IE = 0 EI INTyy servicing IE = 0 INTzz servicing
INTxx (PR = 1)
RETI
During interrupt INTxx servicing, two interrupt requests, INTyy and INTzz are acknowledged, and multiple interrupt servicing is generated. An EI instruction is issued before each interrupt request acknowledgment, and the interrupt request acknowledgment enabled state is set. Example 2. Multiple interrupt servicing is not generated due to priority control
Main processing INTxx servicing INTyy servicing
EI
IE = 0 EI INTyy (PR = 1) RETI
INTxx (PR = 0)
1 instruction execution
IE = 0
RETI
The interrupt request INTyy generated during interrupt INTxx servicing is not acknowledged because its interrupt priority is lower than that of INTxx, and multiple interrupt servicing is not generated. The INTyy request is held pending and acknowledged after execution of 1 instruction of the main processing. PR = 0: Higher priority level PR = 1: Lower priority level IE = 0: Interrupt request acknowledgment disabled
354
User's Manual U11302EJ4V0UM
CHAPTER 16
INTERRUPT AND TEST FUNCTIONS
Figure 16-15. Multiple Interrupt Servicing Example (2/2) Example 3. Multiple interrupt servicing is not generated because interrupts are not enabled
Main processing INTxx servicing IE = 0 INTyy (PR = 0) RETI INTyy servicing
EI
INTxx (PR = 0)
1 instruction execution
IE = 0
RETI
Because interrupts are not enabled in interrupt INTxx servicing (an EI instruction is not issued), interrupt request INTyy is not acknowledged, and multiple interrupt servicing is not generated. The INTyy request is held pending and acknowledged after execution of 1 instruction of the main processing. PR = 0: Higher priority level IE = 0: Interrupt request acknowledgment disabled
User's Manual U11302EJ4V0UM
355
CHAPTER 16
INTERRUPT AND TEST FUNCTIONS
16.4.5 Interrupt request hold Some instructions hold an interrupt request, if any, pending until the completion of execution of the next instruction. These instructions (that hold an interrupt request pending) are listed below. * MOV * MOV * MOV * MOV1 * MOV1 * AND1 * OR1 * XOR1 * SET1 * CLR1 * RETB * RETI * PUSH * POP * BT * BF * EI * DI * Manipulation instructions for IF0L, IF0H, MK0L, MK0H, PR0L, PR0H and INTM0 registers Caution The BRK instruction does not belong to the above group of instructions. However, the software interrupt that is started by execution of the BRK instruction clears the IE flag to 0. Therefore, even if a maskable interrupt request is generated, it is not acknowledged when the BRK instruction is executed. However, a non-maskable interrupt request is acknowledged. The timing at which interrupt requests are held pending is shown in Figure 16-16. Figure 16-16. Interrupt Request Hold
Save PSW and PC, jump to interrupt servicing Interrupt servicing program
PSW, #byte A, PSW PSW, A PSW.bit, CY CY, PSW.bit CY, PSW.bit CY, PSW.bit CY, PSW.bit PSW.bit PSW.bit
PSW PSW PSW.bit, $addr16 PSW.bit, $addr16
* BTCLR PSW.bit, $addr16
CPU processing
Instruction N
Instruction M
xxIF
Remarks 1. Instruction N: Interrupt request hold instruction 2. Instruction M: Instruction other than interrupt request hold instruction 3. The xxPR (priority level) values do not affect the operation of xxIF (interrupt request).
356
User's Manual U11302EJ4V0UM
CHAPTER 16
INTERRUPT AND TEST FUNCTIONS
16.5 Test Functions
The internal test input flag (WTIF) is set to 1 and a standby release signal is generated when the watch timer overflows. Unlike the interrupt function, this function does not perform vector processing. The basic configuration is shown in Figure 16-17. Figure 16-17. Basic Configuration of Test Function
Internal bus
MK
Test input source (INTWT)
IF
Standby release signal
IF:
Test input flag
MK: Test mask flag 16.5.1 Test function control registers The test function is controlled by the following two registers. * Interrupt request flag register 0H (IF0H) * Interrupt mask flag register 0H (MK0H) The names of the test input flag and test mask flag corresponding to the test input signal name are as follows.
Test Input Signal Name INTWT Test Input Flag WTIF Test Mask Flag WTMK
User's Manual U11302EJ4V0UM
357
CHAPTER 16
INTERRUPT AND TEST FUNCTIONS
(1) Interrupt request flag register (IF0H) This register indicates whether a watch timer overflow is detected or not. IF0H is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears IF0H to 00H. Figure 16-18. Format of Interrupt Request Flag Register 0H
Symbol IF0H 7 0 6 0 <5> WTIF <4> KSIF <3> ADIF <2> <1> <0> Address FFE1H After reset 00H R/W R/W
TMIF2 TMIF1 TMIF0
WTIF 0 1
Watch timer overflow detection flag No detection Detection
(2) Interrupt mask flag register (MK0H) This register is used to set the standby mode enable/disable at the time the standby mode is released by the watch timer. MK0H is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets MK0H to FFH. Figure 16-19. Format of Interrupt Mask Flag Register 0H
Symbol MK0H 7 1 6 1 <5> <4> <3> <2> <1> <0> Address FFE5H After reset FFH R/W R/W
WTMK KSMK ADMK TMMK2 TMMK1 TMMK0
WTMK Standby mode control by watch timer 0 1 Standby mode release enabled Standby mode release disabled
16.5.2 Test input signal acknowledgment operation The internal test input signal (INTWT) is generated when the watch timer overflows. This signal sets the WTIF flag. At this time, the standby release signal is generated if it is not masked by the interrupt mask flag (WTMK). By checking the WTIF flag in a cycle shorter than the overflow cycle of the watch timer, a watch function can be realized.
358
User's Manual U11302EJ4V0UM
CHAPTER 17 STANDBY FUNCTION
17.1 Standby Function and Configuration
17.1.1 Standby function The standby function is used to decrease the power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock stops. The system clock oscillator continues oscillation. In this mode, the power consumption cannot be decreased as much as in the STOP mode, but the HALT mode is effective for restarting immediately upon interrupt request and carrying out intermittent operations like clock operations. (2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the main system clock oscillator stops and the whole system stops, so the CPU power consumption can be considerably decreased. Data memory low-voltage hold (down to VDD = 2 V) is possible. Thus, the STOP mode is effective for holding data memory contents with ultra-low power consumption. Because this mode can be released by an interrupt request, it enables intermittent operations to be carried out. However, because a wait time is necessary to secure the oscillation stabilization time after the STOP mode is released, select the HALT mode if it is necessary to start processing immediately upon interrupt request. In either mode, all the contents of the registers, flags, and data memory just before standby mode is set are held. The I/O port output latch and output buffer statuses are also held. Cautions 1. The STOP mode can be used only when the system operates with the main system clock (subsystem clock oscillation cannot be stopped). The HALT mode can be used with either the main system clock or the subsystem clock. 2. When proceeding to the STOP mode, be sure to stop the peripheral hardware operation operated with the main system clock and execute the STOP instruction. 3. To reduce the power consumption of the A/D converter, set bit 7 (CS) of the A/D converter mode register (ADM) to 0 to stop the A/D converter's operation before executing the HALT or STOP instruction.
User's Manual U11302EJ4V0UM
359
CHAPTER 17
STANDBY FUNCTION
17.1.2 Standby function control register The wait time after the STOP mode is released by an interrupt request until the oscillation stabilizes is controlled by the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H. Therefore, when the STOP mode is released by RESET input, the time until it is released is 2 17/fx. Figure 17-1. Format of Oscillation Stabilization Time Select Register
Symbol OSTS
7 0
6 0
5 0
4 0
3 0
2
1
0
Address FFFAH
After reset 04H
R/W R/W
OSTS2 OSTS1 OSTS0
OSTS2 OSTS1 OSTS0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0
Selection of oscillation stabilization time after STOP mode is released
212/fX (819 s) 214/fX (3.28 ms) 215/fX (6.55 ms) 216/fX (13.1 ms) 217/fX (26.2 ms) Setting prohibited
Other than above
Caution The wait time after STOP mode release does not include the time from STOP mode release to clock oscillation start (see "a" below), regardless of whether the STOP mode is released by RESET input or by interrupt request generation.
STOP mode release X1 pin voltage waveform a VSS
Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 5.0 MHz.
360
User's Manual U11302EJ4V0UM
CHAPTER 17
STANDBY FUNCTION
17.2 Standby Function Operations
17.2.1 HALT mode (1) HALT mode set and operating status The HALT mode is set by executing the HALT instruction. It can be set during main system clock or the subsystem clock operation. The operating status in the HALT mode is described below. Table 17-1. HALT Mode Operating Status
HALT Mode Setting Item Clock generator CPU Ports (output latch) 16-bit timer/event counter 8-bit timer/event counter Watchdog timer A/D converter Operation stopped Operation stopped Watch timer Operation enabled when fX/28 is selected for the count clock. Operation enabled when fX/23 to fX/28 is selected for the output clock. Operation enabled Operation disabled Operation enabled Operation enabled when external SCK is selected. Operation enabled Operation enabled when fXT is selected for the count clock. Operation enabled when fXT is selected for the output clock. BUZ is low level. When HALT Instruction Is Executed During Main System Clock Operation Without Subsystem ClockNote 1 With Subsystem ClockNote 2 When HALT Instruction Is Executed During Subsystem Clock Operation When Main System Clock Oscillation Continues When Main System Clock Oscillation Stops
Both main system clock and subsystem clock can be oscillated. Clock supply to the CPU stops. Operation stopped Status before HALT instruction execution is held. Operation enabled Operation stopped Operation enabled when TI1 and TI2 are selected for the count clock.
Clock output
Operation enabled
Buzzer output VFD controller/driver Serial interface Other than automatic transmit/ receive function Automatic transmit/ receive function External interrupts INTP0 INTP1 to INTP3
Operation stopped
Operation enabled when the clock for the peripheral hardware (fx/26 or fx/27) is selected as the sampling clock. Operation enabled
Operation stopped
Notes 1. Including the case where an external clock is not supplied as the subsystem clock 2. Including the case where an external clock is supplied as the subsystem clock
User's Manual U11302EJ4V0UM
361
CHAPTER 17
STANDBY FUNCTION
(2) HALT mode release The HALT mode can be released by the following four sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt request acknowledgment is enabled, vectored interrupt servicing is carried out. If disabled, the instruction at the next address is executed. Figure 17-2. HALT Mode Release by Interrupt Request Generation
Interrupt request HALT instruction Standby release signal Operating mode
Wait
HALT mode
Wait Oscillation
Operating mode
Clock
Remarks 1. The broken line indicates the case when the interrupt request which has released the standby status is acknowledged. 2. Wait time will be as follows. * When vectored interrupt servicing is carried out: 8 to 9 clocks * When vectored interrupt servicing is not carried out: 2 to 3 clocks (b) Release by non-maskable interrupt request When a non-maskable interrupt request is generated, the HALT mode is released and vectored interrupt servicing is carried out regardless of whether interrupt request acknowledgment is enabled or disabled. However, a non-maskable interrupt request is not generated during subsystem clock operation. (c) Release by unmasked test input When an unmasked test signal is input, the HALT mode is released and the instruction at the next address to the HALT instruction is executed.
362
User's Manual U11302EJ4V0UM
CHAPTER 17
STANDBY FUNCTION
(d) Release by RESET input When a RESET signal is input, the HALT mode is released. As is the case with a normal reset operation, the program is executed after branch to the reset vector address. Figure 17-3. HALT Mode Release by RESET Input
HALT instruction
Wait (217/fX: 26.2 ms)
RESET signal Operating mode Reset period
Oscillation stop
HALT mode Oscillation
Oscillation stabilization wait status Oscillation
Operating mode
Clock
Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 5.0 MHz. Table 17-2. Operation After HALT Mode Release
Release Source Maskable interrupt request MKxx 0 0 0 0 0 1 Non-maskable interrupt request Test input - 0 1 RESET input - PRxx 0 0 1 1 1 x - - - - IE 0 1 0 x 1 x x x x x ISP x x 1 0 1 x x x x x Interrupt servicing HALT mode hold Interrupt servicing Next address instruction execution HALT mode hold Reset processing Operation Next address instruction execution Interrupt servicing Next address instruction execution
x: don't care
User's Manual U11302EJ4V0UM
363
CHAPTER 17
STANDBY FUNCTION
17.2.2 STOP mode (1) STOP mode set and operating status The STOP mode is set by executing the STOP instruction. It can be set only during main system clock operation. Cautions 1. When the STOP mode is set, the X2 pin is internally connected to VDD via a pull-up resistor to suppress the leakage at the crystal oscillator. Thus, do not use the STOP mode in a system where an external clock is used for the main system clock. 2. Because the interrupt request signal is used to release the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately released if set. Thus, the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction. After the wait set using the oscillation stabilization time select register (OSTS), the operating mode is set. The operating status in the STOP mode is described below. Table 17-3. STOP Mode Operating Status
STOP Mode Setting Item Clock generator CPU Output ports (output latches) 16-bit timer/event counter 8-bit timer/event counter Watchdog timer A/D converter Watch timer Operation enabled only when fXT is selected for the count clock. Operation enabled when fXT is selected for the output clock. BUZ is low level. Operation disabled Operation enabled only when external input clock is selected as serial clock. Operation stopped Only main system clock stops oscillation. Operation stopped Status before STOP instruction execution is held. Operation stopped Operation enabled only when TI1 and TI2 are selected for the count clock. Operation stopped With Subsystem Clock Without Subsystem Clock
Clock output
PCL is low level.
Buzzer output VFD controller/driver Serial interface Other than automatic transmit/receive function Automatic transmit/ receive function External interrupts INTP0 INTP1 to INTP3
Operation stopped
Operation disabled Operation enabled
364
User's Manual U11302EJ4V0UM
CHAPTER 17
STANDBY FUNCTION
(2) STOP mode release The STOP mode can be released by the following three sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. If interrupt request acknowledgment is enabled after the lapse of oscillation stabilization time, vectored interrupt servicing is carried out. If interrupt request acknowledgment is disabled, the instruction at the next address is executed. Figure 17-4. STOP Mode Release by Interrupt Request Generation
Interrupt request STOP instruction Standby release signal Operating mode Oscillation Oscillation stabilization wait status Oscillation Operating mode Wait (time set by OSTS)
STOP mode Oscillation stop
Clock
Remark The broken line indicates the case when the interrupt request which has released the standby status is acknowledged. (b) Release by unmasked test input When an unmasked test signal is input, the STOP mode is released. After the lapse of oscillation stabilization time, the instruction at the next address to the STOP instruction is executed.
User's Manual U11302EJ4V0UM
365
CHAPTER 17
STANDBY FUNCTION
(c) Release by RESET input When a RESET signal is input, the STOP mode is released. After the lapse of oscillation stabilization time, a reset operation is carried out. Figure 17-5. STOP Mode Release by RESET Input
Wait (217/fX: 26.2 ms)
STOP instruction RESET signal Operating mode Oscillation Reset period
STOP mode Oscillation stop
Oscillation stabilization wait status Oscillation
Operating mode
Clock
Remarks 1. fX: Main system clock oscillation frequency 2. Figures in parentheses apply to operation with fX = 5.0 MHz.
Table 17-4. Operation After STOP Mode Release
Release Source Maskable interrupt request MKxx 0 0 0 0 0 1 Test input 0 1 RESET input - PRxx 0 0 1 1 1 x - - - IE 0 1 0 x 1 x x x x ISP x x 1 0 1 x x x x Interrupt servicing STOP mode hold Next address instruction execution STOP mode hold Reset processing Operation Next address instruction execution Interrupt servicing Next address instruction execution
x: don't care
366
User's Manual U11302EJ4V0UM
CHAPTER 18 RESET FUNCTION
18.1 Reset Function
The following two operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop time detection External reset and internal reset have no functional differences. In both cases, program execution starts at addresses 0000H and 0001H by RESET input. When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware is set to the status as shown in Table 18-1. Each pin is high impedance during reset input or during the oscillation stabilization time just after reset release. When a high level is input to the RESET pin, the reset is released and program execution starts after the lapse of the oscillation stabilization time (2 17/fX). The reset applied by watchdog timer overflow is automatically released after the reset and program execution starts after the lapse of the oscillation stabilization time (217/fX) (see Figures 18-2 to 18-4). Cautions 1. For an external reset, input a low level to the RESET pin for 10 s or more. 2. During reset input, main system clock oscillation remains stopped but subsystem clock oscillation continues. 3. When the STOP mode is released by reset, the STOP mode contents are held during reset input. However, the port pins become high impedance.
Figure 18-1. Block Diagram of Reset Function
RESET
Reset controller
Reset signal
Overflow Count clock Watchdog timer Stop
Interrupt function
User's Manual U11302EJ4V0UM
367
CHAPTER 18
RESET FUNCTION
Figure 18-2. Timing of Reset by RESET Input
X1 Normal operation RESET Reset period (oscillation stop) Oscillation stabilization time wait Normal operation (reset processing)
Internal reset signal Delay Port pin Delay Hi-Z
Figure 18-3. Timing of Reset due to Watchdog Timer Overflow
X1 Normal operation Watchdog timer overflow Reset period (oscillation stop) Oscillation stabilization time wait Normal operation (reset processing)
Internal reset signal
Port pin
Hi-Z
Figure 18-4. Timing of Reset by RESET Input in STOP Mode
X1 STOP instruction execution Normal operation RESET
Stop status (oscillation stop)
Reset period (oscillation stop)
Oscillation stabilization time wait
Normal operation (reset processing)
Internal reset signal Delay Port pin Delay Hi-Z
368
User's Manual U11302EJ4V0UM
CHAPTER 18
RESET FUNCTION
Table 18-1. Hardware Status After Reset (1/2)
Hardware Program counter (PC) Note 1 Status After Reset The contents of reset vector tables (0000H and 0001H) are set. Undefined 02H Data memory General-purpose registers Ports (output latches) Port mode registers Ports 0 to 3, 7 to 12 (P0 to P3, P7 to P12) (PM0, PM7) (PM1, PM2, PM3, PM10, PM11, PM12) Pull-up resistor option register (PUO) Processor clock control register (PCC) Internal memory size switching register (IMS) Internal expansion RAM size switching register (IXS) Oscillation stabilization time select register (OSTS) 16-bit timer/event counter Timer register (TM0) Compare register (CR00) Capture register (CR01) Clock select register (TCL0) Mode control register (TMC0) Output control register (TOC0) 8-bit timer/event counter Timer registers (TM1, TM2) Compare registers (CR10, CR20) Clock select register (TCL1) Mode control registers (TMC1, TMC2) Output control register (TOC1) Undefined Note 2 Undefined Note 2 00H 1FH FFH 00H 04H Note 3 Note 3 04H 00H Undefined Undefined 00H 00H 00H 00H Undefined 00H 00H 00H
Stack pointer (SP) Program status word (PSW) RAM
Notes 1. During reset input or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. 2. If the reset is applied in the standby mode, the status before reset will be held after reset. 3. The after-reset values of the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS) depend on the product.
PD780204
IMS IXS C8H None
PD780204A
CFH
PD780205
CAH
PD780205A
CFH
PD780206
CCH 0AH
PD780208 PD78P0208
CFH CFH
User's Manual U11302EJ4V0UM
369
CHAPTER 18
RESET FUNCTION
Table 18-1. Hardware Status After Reset (2/2)
Hardware Watch timer Watchdog timer Mode register (WDTM) Serial interface Clock select register (TCL3) Shift registers (SIO0, SIO1) Mode registers (CSIM0, CSIM1) Serial bus interface control register (SBIC) Slave address register (SVA) Automatic data transmit/receive control register (ADTC) Automatic data transmit/receive address pointer (ADTP) Automatic data transmit/receive interval specification register (ADTI) Interrupt timing specification register (SINT) A/D converter Mode register (ADM) Conversion result register (ADCR) Input select register (ADIS) VFD controller/driver Display mode register 0 (DSPM0) Display mode register 1 (DSPM1) Display mode register 2 (DSPM2) Interrupts Request flag registers (IF0L, IF0H) Mask flag registers (MK0L, MK0H) Priority specification flag registers (PR0L, PR0H) External interrupt mode register (INTM0) Sampling clock select register (SCS) 00H 88H Undefined 00H 00H Undefined 00H 00H 00H 00H 01H Undefined 00H 00H 00H 00H 00H FFH FFH 00H 00H Clock select register (TCL2) Status After Reset 00H
370
User's Manual U11302EJ4V0UM
CHAPTER 19 PD78P0208
The PD78P0208 is a product integrating a one-time programmable ROM (one-time PROM). Table 191 shows the differences between the PD78P0208 and the mask ROM versions (PD780204, 780204A, 780205, 780205A, 780206, and 780208). Table 19-1. Differences Between PD78P0208 and Mask ROM Versions
Item Internal ROM configuration Internal ROM capacity
PD78P0208
One-time PROM 60 KB
Mask ROM Versions Mask ROM
PD780204: PD780204A: PD780205: PD780205A: PD780206: PD780208: PD780204: PD780204A: PD780205: PD780205A: PD780206: PD780208:
Impossible
32 32 40 40 48 60
KB KB KB KB KB KB
Internal expansion RAM capacity
1024 bytes
None None None None 1024 bytes 1024 bytes
Change in capacity of internal ROM by means of internal memory size switching register (IMS) Internal expansion RAM size switching register (IXS)
Possible Note 1
Provided (Internal expansion RAM capacity can be changed using IXS Note 2.)
PD780204, 780204A, PD780205, 780205A: Not provided PD780206, 780208: Provided (However, internal expansion RAM capacity cannot be changed.)
Provided None On-chip pull-down resistors can be specified in 1-bit units by mask option. On-chip pull-up resistors can be specified in 1-bit units by mask option. On-chip pull-down resistors can be specified in 1-bit units by mask option. On-chip pull-down resistors can be specified in 1-bit units by mask option. Pull-down resistors can be specified to be connected to either VLOAD or VSS in 4bit units from P80.
IC pin VPP pin P30/TO0 to P32/TO2, P33/TI1, P34/TI2, P35/PCL, P36/BUZ, P37 P70 to P74 FIP0 to FIP12 P80/FIP13 to P87/FIP20, P90/FIP21 to P97/FIP28, P100/FIP29 to P107/FIP36, P110/FIP37 to P117/FIP44, P120/FIP45 to P127/FIP52 Electrical specifications
None Provided On-chip pull-down resistors are not provided. On-chip pull-up resistors are not provided. On-chip pull-down resistors are provided (connected to VLOAD). On-chip pull-down resistors are not provided.
Refer to the separate data sheet.
Notes 1. After RESET input, the internal PROM capacity is set to 60 KB. 2. After RESET input, the internal expansion RAM capacity is set to 1024 bytes. Caution There are differences in noise immunity and noise radiation between the PROM and mask ROM versions. When pre-producing an application set with the PROM version and then massproducing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask ROM version.
User's Manual U11302EJ4V0UM
371
CHAPTER 19
PD78P0208
19.1 Internal Memory Size Switching Register
The internal memory capacity of the PD78P0208 can be selected by using the internal memory size switching register (IMS). The same memory map as that of the mask ROM version with a different internal memory capacity is possible by setting IMS. IMS is set with an 8-bit memory manipulation instruction. RESET input sets IMS as shown in Table 19-2.
372
User's Manual U11302EJ4V0UM
CHAPTER 19
PD78P0208
Figure 19-1. Format of Internal Memory Size Switching Register (IMS)
Symbol
7
6
5
4 0
3
2
1
0
Address After reset FFF0H Note
R/W R/W
IMS RAM2 RAM1 RAM0
ROM3 ROM2 ROM1 ROM0
ROM3 ROM2 ROM1 ROM0 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 1
Internal ROM capacity selection
32 KB 40 KB 48 KB 60 KB Setting prohibited
Other than above
RAM2 RAM1 RAM0 1 1 0
Internal high-speed RAM capacity selection
1024 bytes Setting prohibited
Other than above
Note
The value of the internal memory size switching register after reset differs depending on the product (see Table 19-2). Table 19-2 lists the IMS setting values for a memory map equivalent to the mask ROM versions. Table 19-2. Internal Memory Size Switching Register Setting Values
Target Product IMS Value After Reset C8H CFH CAH CFH CCH CFH CFH CAH C8H IMS Setting Value
PD780204 PD780204A PD780205 PD780205A PD780206 PD780208 PD78P0208
Caution
When using the PD780204, 780205, 780206, and 780208, do not set any value other than the above IMS Value After Reset to IMS. When using the PD780204A and 780205A, be sure to set the IMS Setting Value shown in Table 19-2 to IMS.
User's Manual U11302EJ4V0UM
373
CHAPTER 19
PD78P0208
19.2
Internal Expansion RAM Size Switching Register
By setting the internal expansion RAM size swtiching register (IXS), the PD78P0208 can have the same memory map as used in mask ROM versions that have a different internal expansion RAM capacity. For the mask ROM versions, IXS does not need to be set. IXS is set with an 8-bit memory manipulation instruction. RESET input sets IXS to 0AH. Cautions 1. The internal expansion RAM size switching register (IXS) is only incorporated in the
PD780206, PD780208, and PD78P0208.
2. When using a mask ROM version PD780204, PD780204A, PD780205, PD780205A,
PD780206, PD780208, do not set a value other than those listed in Table 19-3 to IXS.
Figure 19-2. Format of Internal Expansion RAM Size Switching Register
Symbol IXS
7 0
6 0
5 0
4 0
3
IX RAM3
2
IX RAM2
1
IX RAM1
0
IX RAM0
Address FFF4H
After reset 0AH
R/W W
Internal expansion RAM IX IX IX IX RAM3 RAM2 RAM1 RAM0 capacity selection 1 1 0 1 1 0 0 0 1024 bytes No internal expansion RAM (0 bytes) Setting prohibited
Other than above
Table 19-3 lists the IXS setting values for a memory map equivalent to the mask ROM versions. Table 19-3. Internal Expansion RAM Size Switching Register Setting Values
Target Mask ROM Version IXS Setting Value 0CH
PD780204, 780204A PD780205, 780205A PD780206 PD780208
0AH
IXS is not incorporated in the PD780204, PD780204A, PD780205, and PD780205A. However, if a write instruction to IXS is executed in the PD780204, PD780204A, PD780205, or
PD780205A, the operation is not affected.
374
User's Manual U11302EJ4V0UM
CHAPTER 19
PD78P0208
19.3 PROM Programming
The PD78P0208 incorporates a 60 KB PROM as program memory. to 1.5 Pin Configuration (Top View) (2) PROM programming mode. Caution Programs must be written in addresses 0000H to EFFFH (the last address EFFFH must be specified). Programs cannot be written by a PROM programmer that cannot specify the write address. 19.3.1 Operating modes When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, the When programming, the PROM
programming mode is set by means of the VPP pin and the RESET pin. For the connection of unused pins, refer
PD78P0208 is set to the PROM programming mode. This is one of the operating modes shown in Table 194 below according to the setting of the CE, OE, and PGM pins. The PROM contents can be read by setting the read mode. Table 19-4. PROM Programming Operating Modes
Pin RESET Operating Mode Page data latch Page write Byte write Program verify Program inhibit L +12.5 V +6.5 V H H L L x x Read Output disabled Standby +5 V +5 V L L H L H H L H L L H x H L L H H L H x x Data output High impedance High impedance Data input High impedance Data input Data output High impedance VPP VDD CE OE PGM D0 to D7
x: L or H (1) Read mode Read mode is set by setting CE to L and OE to L. (2) Output disabled mode If OE is set to H, data output becomes high impedance and the output disabled mode is set. Therefore, if multiple PD78P0208s are connected to the data bus, data can be read from any one device by controlling the OE pin. (3) Standby mode Setting CE to H sets the standby mode. In this mode, data output becomes high impedance irrespective of the status of OE.
User's Manual U11302EJ4V0UM
375
CHAPTER 19
PD78P0208
(4) Page data latch mode Setting CE to H, PGM to H, and OE to L at the start of the page write mode sets the page data latch mode. In this mode, 1-page 4-byte data is latched in the internal address/data latch circuit. (5) Page write mode After a 1-page 4-byte address and data are latched by the page data latch mode, a page write is executed by applying a 0.1 ms program pulse (active-low) to the PGM pin while CE = H and OE = H. After this, program verification can be performed by setting CE to L and OE to L. If programming is not performed by one program pulse, repeated write and verify operations are executed X times (X 10). (6) Byte write mode A byte write is executed by applying a 0.1 ms program pulse (active-low) to the PGM pin while CE = L and OE = H. After this, program verification can be performed by setting OE to L. If programming is not performed by one program pulse, repeated write and verify operations are executed X times (X 10). (7) Program verify mode Setting CE to L, PGM to H, and OE to L sets the program verify mode. After writing is performed, this mode should be used to check whether the data was written correctly. (8) Program inhibit mode The program inhibit mode is used when the OE, VPP, and D0 to D7 pins of multiple PD78P0208s are connected in parallel, and when you wish to write to one of these devices. The page write mode or byte write mode described above is used to perform a write. At this time, the write is not performed on the device which has the PGM pin driven high.
376
User's Manual U11302EJ4V0UM
CHAPTER 19
PD78P0208
19.3.2 PROM write procedure Figure 19-3. Page Program Mode Flowchart
Start Address = G VDD = 6.5 V, VPP = 12.5 V
X=0 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Latch No X = 10? 0.1 ms program pulse Fail Yes
Address = Address + 1
X=X+1
Verify 4 bytes Pass No Address = N? Yes VDD = 4.5 to 5.5 V, VPP = VDD
Pass
All bytes verified? All pass
Fail
End of write
Defective product
G = Start address N = Last address of program
User's Manual U11302EJ4V0UM
377
CHAPTER 19
PD78P0208
Figure 19-4. Page Program Mode Timing
Page data latch
Page program
Program verify
A2 to A16
A0, A1
D0 to D7 Data input VPP VPP VDD VDD + 1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL Data output
378
User's Manual U11302EJ4V0UM
CHAPTER 19
PD78P0208
Figure 19-5. Byte Program Mode Flowchart
Start Address = G VDD = 6.5 V, VPP = 12.5 V
X=0
X=X+1 0.1 ms program pulse
No X = 10? Yes
Address = Address + 1
Verify Pass No Address = N? Yes VDD = 4.5 to 5.5 V, VPP = VDD
Fail
Pass
All bytes verified All pass
Fail
End of write
Defective product
G = Start address N = Last address of program
User's Manual U11302EJ4V0UM
379
CHAPTER 19
PD78P0208
Figure 19-6. Byte Program Mode Timing
Program Program verify
A0 to A16
D0 to D7
Data input
Data output
VPP VPP VDD
VDD + 1.5 VDD VDD
VIH CE VIL VIH PGM VIL VIH OE VIL
Cautions 1. Ensure that VDD is applied before VPP and removed after VPP. 2. Ensure that VPP does not exceed +13.5 V including overshoot. 3. Disconnecting the device while +12.5 V is being applied to VPP may have an adverse affect on reliability.
380
User's Manual U11302EJ4V0UM
CHAPTER 19
PD78P0208
19.3.3 PROM read procedure PROM contents can be read onto the external data bus (D0 to D7) using the following procedure. (1) Fix the RESET pin low, and supply +5 V to the VPP pin. Unused pins are handled as shown in 1.5 Pin Configuration (Top View) (2) PROM programming mode. (2) Supply +5 V to the VDD and VPP pins. (3) Input the address of the data to be read to pins A0 to A16. (4) Read mode. (5) Output data to pins D0 to D7. The timing for steps (2) through (5) above is shown in Figure 19-7. Figure 19-7. PROM Read Timing
A0 to A16
Address input
CE (input)
OE (input)
Hi-Z D0 to D7 Data output
Hi-Z
User's Manual U11302EJ4V0UM
381
CHAPTER 19
PD78P0208
19.4
Screening of One-Time PROM Version
A one-time PROM device (PD78P0208GF-3BA) cannot be fully tested by NEC Electronics before shipment due to the nature of PROM. After the necessary data has been written, it is recommended to implement a screening process, that is, the written contents should be verified after the device has been stored under the following high-temperature conditions.
Storage Temperature 125C
Storage Time 24 hours
382
User's Manual U11302EJ4V0UM
CHAPTER 20 INSTRUCTION SET
This chapter describes the instruction set for the PD780208 Subseries. For details of the operations and mnemonics (instruction codes) of each instruction, refer to the 78K/0 Series Instructions User's Manual (U12326E).
User's Manual U11302EJ4V0UM
383
CHAPTER 20
INSTRUCTION SET
20.1 Conventions
20.1.1 Operand identifiers and description methods Operands are described in the "Operand" column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more description methods, select one of them. Uppercase letters and the symbols #, !, $, and [ ] are keywords and are described as they are. Each symbol has the following meaning. * #: * !: * $: Immediate data specification Absolute address specification Relative address specification
* [ ]: Indirect address specification In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #, !, $, and [ ] symbols. For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for description. Table 20-1. Operand Identifiers and Description Methods
Identifier r rp sfr sfrp saddr saddrp addr16 addr11 addr5 word byte bit RBn Description Method X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special-function register symbolNote Special-function register symbol (16-bit manipulatable register, even addresses only)Note FE20H to FF1FH Immediate data or label FE20H to FF1FH Immediate data or label (even addresses only) 0000H to FFFFH Immediate data or label (only even addresses for 16-bit data transfer instructions) 0800H to 0FFFH Immediate data or label 0040H to 007FH Immediate data or label (even addresses only) 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label RB0 to RB3
Note FFD0H to FFDFH cannot be addressed. Remark For special-function register symbols, see Table 3-3 Special-Function Register List.
384
User's Manual U11302EJ4V0UM
CHAPTER 20
INSTRUCTION SET
20.1.2 Description of "operation" column A: X: B: C: D: E: H: L: AX: BC: DE: HL: PC: SP: PSW: CY: AC: Z: RBS: IE: NMIS: ( : : : : jdisp8: ): XH, XL: A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Register bank select flag Interrupt request enable flag Non-maskable interrupt servicing flag Memory contents indicated by address or register contents in parentheses Higher 8 bits and lower 8 bits of 16-bit register Logical product (AND) Logical sum (OR) Exclusive logical sum (exclusive OR) Inverted data Signed 8-bit data (displacement value)
addr16: 16-bit immediate data or label
20.1.3 Description of "flag operation" column (Blank): Unchanged 0: 1: x: R: Cleared to 0 Set to 1 Set/cleared according to the result Previously saved value is restored
User's Manual U11302EJ4V0UM
385
CHAPTER 20
INSTRUCTION SET
20.2 Operation List
Instruc- Mnemonic tion Group MOV 8-bit data transfer Operands Bytes Clocks Note 1 r, #byte saddr, #byte sfr, #byte A, r r, A A, saddr saddr, A A, sfr sfr, A A, !addr16 !addr16, A PSW, #byte A, PSW PSW, A A, [DE] [DE], A A, [HL] [HL], A A, [HL+byte] [HL+byte], A A, [HL+B] [HL+B], A A, [HL+C] [HL+C], A XCH A, r A, saddr A, sfr A, !addr16 A, [DE] A, [HL] A, [HL+byte] A, [HL+B] A, [HL+C]
Note 3 Note 3 Note 3
Operation
Flag Z AC CY
Note 2 - 7 7 - - 5 5 5 5 9 9 7 5 5 5 5 5 5 9 9 7 7 7 7 - 6 6 10 6 6 10 10 10 r byte (saddr) byte sfr byte Ar rA A (saddr) (saddr) A A sfr sfr A A (addr16) (addr16) A PSW byte A PSW PSW A A (DE) (DE) A A (HL) (HL) A A (HL+byte) (HL+byte) A A (HL+B) (HL+B) A A (HL+C) (HL+C) A Ar A (saddr) A sfr A (addr16) A (DE) A (HL) A (HL+byte) A (HL+B) A (HL+C)
2 3 3 1 1 2 2 2 2 3 3 3 2 2 1 1 1 1 2 2 1 1 1 1 1 2 2 3 1 1 2 2 2
4 6 - 2 2 4 4 - - 8 8 - - - 4 4 4 4 8 8 6 6 6 6 2 4 - 8 4 4 8 8 8
x x
x x
x x
Notes 1. When the internal high-speed RAM area is accessed or an instruction with no data access. 2. When an area except the internal high-speed RAM area is accessed. 3. Except r = A Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC).
386
User's Manual U11302EJ4V0UM
CHAPTER 20
INSTRUCTION SET
Instruc- Mnemonic tion Group MOVW 16-bit data transfer
Operands
Bytes
Clocks Note 1 Note 2 - 10 10 8 8 8 8 - - 12 12 - - 8 - - 5 9 5 9 9 9 - 8 - - 5 9 5 9 9 9 rp word
Operation
Flag Z AC CY
rp, #word saddrp, #word sfrp, #word AX, saddrp saddrp, AX AX, sfrp sfrp, AX AX, rp rp, AX AX, !addr16 !addr16, AX
Note 3 Note 3 Note 3
3 4 4 2 2 2 2 1 1 3 3 1 2 3
Note 4
6 8 - 6 6 - - 4 4 10 10 4 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8
(saddrp) word sfrp word AX (saddrp) (saddrp) AX AX sfrp sfrp AX AX rp rp AX AX (addr16) (addr16) AX AX rp A, CY A+byte (saddr), CY (saddr)+byte A, CY A+r r, CY r+A A, CY A+(saddr) A, CY A+(addr16) A, CY A+(HL) A, CY A+(HL+byte) A, CY A+(HL+B) A, CY A+(HL+C) A, CY A+byte+CY (saddr), CY (saddr)+byte+CY A, CY A+r+CY r, CY r+A+CY A, CY A+(saddr)+CY A, CY A+(addr16)+CY A, CY A+(HL)+CY A, CY A+(HL+byte)+CY A, CY A+(HL+B)+CY A, CY A+(HL+C)+CY x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
XCHW
8-bit operation
AX, rp A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL+byte] A, [HL+B] A, [HL+C]
ADD
2 2 2 3 1 2 2 2 2 3
ADDC
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL+byte] A, [HL+B] A, [HL+C]
Note 4
2 2 2 3 1 2 2 2
Notes 1. When the internal high-speed RAM area is accessed or an instruction with no data access. 2. When an area except the internal high-speed RAM area is accessed. 3. Only when rp = BC, DE, or HL 4. Except r = A Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC).
User's Manual U11302EJ4V0UM
387
CHAPTER 20
INSTRUCTION SET
Instruc- Mnemonic tion Group
8-bit operation
Operands
Bytes
Clocks Note 1 Note 2 - 8 - - 5 9 5 9 9 9 - 8 - - 5 9 5 9 9 9 - 8 - - 5 9 5 9 9 9
Operation
Flag Z AC CY
SUB
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL+byte] A, [HL+B] A, [HL+C]
Note 3
2 3 2 2 2 3 1 2 2 2 2 3
Note 3
4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8
A, CY A-byte (saddr), CY (saddr)-byte A, CY A-r r, CY r-A A, CY A-(saddr) A, CY A-(addr16) A, CY A-(HL) A, CY A-(HL+byte) A, CY A-(HL+B) A, CY A-(HL+C) A, CY A-byte-CY (saddr), CY (saddr)-byte-CY A, CY A-r-CY r, CY r-A-CY A, CY A-(saddr)-CY A, CY A-(addr16)-CY A, CY A-(HL)-CY A, CY A-(HL+byte)-CY A, CY A-(HL+B)-CY A, CY A-(HL+C)-CY AA AA rr AA AA AA AA AA AA A (saddr) (addr16) (HL) (HL+byte) (HL+B) (HL+C) byte byte (saddr) (saddr) r
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
x x x x x x x x x x x x x x x x x x x x
x x x x x x x x x x x x x x x x x x x x
SUBC
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL+byte] A, [HL+B] A, [HL+C]
2 2 2 3 1 2 2 2 2 3
AND
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL+byte] A, [HL+B] A, [HL+C]
Note 3
2 2 2 3 1 2 2 2
Notes 1. When the internal high-speed RAM area is accessed or an instruction with no data access. 2. When an area except the internal high-speed RAM area is accessed. 3. Except r = A Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC).
388
User's Manual U11302EJ4V0UM
CHAPTER 20
INSTRUCTION SET
Instruc- Mnemonic tion Group
8-bit operation
Operands
Bytes
Clocks Note 1 Note 2 - 8 - - 5 9 5 9 9 9 - 8 - - 5 9 5 9 9 9 - 8 - - 5 9 5 9 9 9 AA AA rr AA AA AA AA AA AA AA AA rr AA AA AA AA AA AA A-byte (saddr)-byte A-r r-A A-(saddr) A-(addr16) A-(HL) A-(HL+byte) A-(HL+B) A-(HL+C) A A byte
Operation
Flag Z AC CY x
OR
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL+byte] A, [HL+B] A, [HL+C]
Note 3
2 3 2 2 2 3 1 2 2 2 2 3
Note 3
4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8 4 6 4 4 4 8 4 8 8 8
(saddr) (saddr) r
byte
x x x x x x x x x x
(saddr) (addr16) (HL) (HL+byte) (HL+B) (HL+C) byte byte
XOR
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL+byte] A, [HL+B] A, [HL+C]
(saddr) (saddr) r
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
2 2 2 3 1 2 2 2 2 3
(saddr) (addr16) (HL) (HL+byte) (HL+B) (HL+C)
CMP
A, #byte saddr, #byte A, r r, A A, saddr A, !addr16 A, [HL] A, [HL+byte] A, [HL+B] A, [HL+C]
Note 3
2 2 2 3 1 2 2 2
Notes 1. When the internal high-speed RAM area is accessed or an instruction with no data access. 2. When an area except the internal high-speed RAM area is accessed. 3. Except r = A Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC).
User's Manual U11302EJ4V0UM
389
CHAPTER 20
INSTRUCTION SET
Instruc- Mnemonic tion Group
16-bit
Operands
Bytes
Clocks Note 1 Note 2 - - - - - - 6 - 6 - - - - - - 12 12
Operation
Flag Z AC CY
ADDW
AX, #word AX, #word AX, #word X C r saddr
3 3 3 2 2 1 2 1 2 1 1 1 1 1 1 2 2
6 6 6 16 25 2 4 2 4 4 4 2 2 2 2 10 10
AX, CY AX+word AX, CY AX-word AX-word AX A x X AX (Quotient), C (Remainder) AX/C r r+1 (saddr) (saddr)+1 r r-1 (saddr) (saddr)-1 rp rp+1 rp rp-1 (CY, A7 A0, Am-1 Am) x 1 (CY, A0 A7, Am+1 Am) x 1 (CY A0, A7 CY, Am-1 Am) x 1 (CY A7, A0 CY, Am+1 Am) x 1 A3-0 (HL)3-0, (HL)7-4 A3-0, (HL)3-0 (HL)7-4 A3-0 (HL)7-4, (HL)3-0 A3-0, (HL)7-4 (HL)3-0 Decimal Adjust Accumulator after Addition
x x x
x x x
x x x
operation SUBW
CMPW
Multiply/ divide Increase/ decrease
MULU DIVUW INC
x x x x
x x x x
DEC INCW DECW
Rotation
r saddr rp rp A, 1 A, 1 A, 1 A, 1 [HL] [HL]
ROR ROL RORC ROLC ROR4 ROL4
x x x x
BCD adjust
ADJBA
2
4
-
x x
x x
x x x x x x x
ADJBS
2
4
-
Decimal Adjust Accumulator after Subtract CY (saddr.bit) CY sfr.bit CY A.bit CY PSW.bit CY (HL).bit (saddr.bit) CY sfr.bit CY A.bit CY PSW.bit CY (HL).bit CY
Bit manipulation
MOV1
CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit saddr.bit, CY sfr.bit, CY A.bit, CY PSW.bit, CY [HL].bit, CY
3 3 2 3 2 3 3 2 3 2
6 - 4 - 6 6 - 4 - 6
7 7 - 7 7 8 8 - 8 8
x
x
Notes 1. When the internal high-speed RAM area is accessed or an instruction with no data access. 2. When an area except the internal high-speed RAM area is accessed. Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC).
390
User's Manual U11302EJ4V0UM
CHAPTER 20
INSTRUCTION SET
Instruc- Mnemonic tion Group AND1 Bit manipulation
Operands
Bytes
Clocks Note 1 Note 2 7 7 - 7 7 7 7 - 7 7 7 7 - 7 7 6 8 - 6 8 6 8 - 6 8 - - - CY CY CY CY CY CY CY CY CY CY CY CY CY CY CY CY CY CY CY CY CY CY CY CY CY CY CY CY CY CY sfr.bit 1 A.bit 1 PSW.bit 1 (HL).bit 1
Operation
Flag Z AC CY
CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit
3 3 2 3 2 3 3 2 3 2 3 3 2 3 2 2 3 2 2 2 2 3 2 2 2 1 1 1
6 - 4 - 6 6 - 4 - 6 6 - 4 - 6 4 - 4 - 6 4 - 4 - 6 2 2 2
(saddr.bit) sfr.bit A.bit PSW.bit (HL).bit (saddr.bit) sfr.bit A.bit PSW.bit (HL).bit (saddr.bit) sfr.bit A.bit PSW.bit (HL).bit
x x x x x x x x x x x x x x x
OR1
CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit
XOR1
CY, saddr.bit CY, sfr.bit CY, A.bit CY, PSW.bit CY, [HL].bit
SET1
saddr.bit sfr.bit A.bit PSW.bit [HL].bit
(saddr.bit) 1
x
x
x
CLR1
saddr.bit sfr.bit A.bit PSW.bit [HL].bit
(saddr.bit) 0 sfr.bit 0 A.bit 0 PSW.bit 0 (HL).bit 0 CY 1 CY 0 CY CY 1 0 x x x x
SET1 CLR1 NOT1
CY CY CY
Notes 1. When the internal high-speed RAM area is accessed or an instruction with no data access. 2. When an area except the internal high-speed RAM area is accessed. Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC).
User's Manual U11302EJ4V0UM
391
CHAPTER 20
INSTRUCTION SET
Instruc- Mnemonic tion Group Call return CALL
Operands
Bytes
Clocks Note 1 Note 2 -
Operation
Flag Z AC CY
!addr16
3
7
(SP-1) (PC+3)H, (SP-2) (PC+3)L, PC addr16, SP SP-2 (SP-1) (PC+2)H, (SP-2) (PC+2)L, PC15-11 00001, PC10-0 addr11, SP SP-2
CALLF
!addr11
2
5
-
CALLT
[addr5]
1
6
-
(SP-1) (PC+1)H, (SP-2) (PC+1)L, PCH (00000000, addr5+1), PCL (00000000, addr5), SP SP-2
BRK
1
6
-
(SP-1) PSW, (SP-2) (PC+1)H, (SP-3) (PC+1)L, PCH (003FH), PCL (003EH), SP SP-3, IE 0
RET
1
6
-
PCH (SP+1), PCL (SP), SP SP+2 PCH (SP+1), PCL (SP), PSW (SP+2), SP SP+3, NMIS 0 R R R
RETI
1
6
-
RETB
1
6
-
PCH (SP+1), PCL (SP), PSW (SP+2), SP SP+3 (SP-1) PSW, SP SP-1 (SP-1) rpH, (SP-2) rpL, SP SP-2 PSW (SP), SP SP+1 rpH (SP+1), rpL (SP), SP SP+2 SP word SP AX AX SP PC addr16 PC PC + 2 + jdisp8 PCH A, PCL X PC PC + 2 + jdisp8 if CY = 1 PC PC + 2 + jdisp8 if CY = 0 PC PC + 2 + jdisp8 if Z = 1 PC PC + 2 + jdisp8 if Z = 0
R
R
R
Stack manipulation
PUSH
PSW rp
1 1
2 4
- -
POP
PSW rp
1 1
2 4
- -
R
R
R
MOVW
SP, #word SP, AX AX, SP
4 2 2 3 2 2 2 2 2 2
- - - 6 6 8 6 6 6 6
10 8 8 - - - - - - -
Uncondi- BR tional branch
!addr16 $addr16 AX
Conditional branch
BC BNC BZ BNZ
$addr16 $addr16 $addr16 $addr16
Notes 1. When the internal high-speed RAM area is accessed or an instruction with no data access. 2. When an area except the internal high-speed RAM area is accessed. Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC).
392
User's Manual U11302EJ4V0UM
CHAPTER 20
INSTRUCTION SET
Instruc- Mnemonic tion Group Conditional branch BT
Operands
Bytes
Clocks Note 1 Note 2 9 11 - 9 11 11 11 - 11 11 12
Operation
Flag Z AC CY
saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16
3 4 3 3 3 4 4 3 4 3 4
8 - 8 - 10 10 - 8 - 10 10
PC PC+3+jdisp8 if (saddr.bit) = 1 PC PC+4+jdisp8 if sfr.bit = 1 PC PC+3+jdisp8 if A.bit = 1 PC PC+3+jdisp8 if PSW.bit = 1 PC PC+3+jdisp8 if (HL).bit = 1 PC PC+4+jdisp8 if (saddr.bit) = 0 PC PC+4+jdisp8 if sfr.bit = 0 PC PC+3+jdisp8 if A.bit = 0 PC PC+4+jdisp8 if PSW.bit = 0 PC PC+3+jdisp8 if (HL).bit = 0 PC PC+4+jdisp8 if (saddr.bit) = 1 then reset (saddr.bit) PC PC+4+jdisp8 if sfr.bit = 1 then reset sfr.bit PC PC+3+jdisp8 if A.bit = 1 then reset A.bit PC PC+4+jdisp8 if PSW.bit = 1 then reset PSW.bit PC PC+3+jdisp8 if (HL).bit = 1 then reset (HL).bit B B-1, then PC PC+2+jdisp8 if B 0 C C-1, then PC PC+2+jdisp8 if C 0 (saddr) (saddr)-1, then PC PC+3+jdisp8 if (saddr) 0 RBS1, 0 n No Operation IE 1 (Enable Interrupt) IE 0 (Disable Interrupt) Set HALT Mode Set STOP Mode x x x
BF
saddr.bit, $addr16 sfr.bit, $addr16 A.bit, $addr16 PSW.bit, $addr16 [HL].bit, $addr16
BTCLR
saddr.bit, $addr16
sfr.bit, $addr16
4
-
12
A.bit, $addr16
3
8
-
PSW.bit, $addr16
4
-
12
[HL].bit, $addr16
3
10
12
DBNZ
B, $addr16
2
6
-
C, $addr16
2
6
-
saddr, $addr16
3
8
10
CPU control
SEL NOP EI DI HALT STOP
RBn
2 1 2 2 2 2
4 2 - - 6 6
- - 6 6 - -
Notes 1. When the internal high-speed RAM area is accessed or an instruction with no data access. 2. When an area except the internal high-speed RAM area is accessed. Remark One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock control register (PCC).
User's Manual U11302EJ4V0UM
393
CHAPTER 20
INSTRUCTION SET
20.3 Instructions Listed by Addressing Type
(1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
394
User's Manual U11302EJ4V0UM
CHAPTER 20
INSTRUCTION SET
Second Operand First Operand A
#byte
A
rNote
sfr
saddr
!addr16
PSW
[DE]
[HL]
[HL+byte] $addr16 [HL+B] [HL+C]
1
None
ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV
MOV XCH
MOV XCH ADD
MOV XCH ADD
ROR ROL RORC ROLC
ADDC ADDC SUB SUB
SUBC SUBC AND OR XOR CMP AND OR XOR CMP INC DEC
r
MOV
MOV ADD ADDC SUB SUBC AND OR XOR CMP
B, C sfr saddr MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP !addr16 PSW MOV MOV MOV MOV MOV
DBNZ
DBNZ
INC DEC
PUSH POP
[DE] [HL]
MOV MOV ROR4 ROL4
[HL+byte] [HL+B] [HL+C] X C
MOV
MULU DIVUW
Note Except r = A
User's Manual U11302EJ4V0UM
395
CHAPTER 20
INSTRUCTION SET
(2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second Operand First Operand AX ADDW SUBW CMPW rp MOVW MOVWNote INCW DECW PUSH POP sfrp saddrp !addr16 SP MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW XCHW MOVW MOVW MOVW MOVW #word AX rpNote sfrp saddrp !addr16 SP None
Note Only when rp = BC, DE, or HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
Second Operand First Operand A.bit MOV1 BT BF BTCLR sfr.bit MOV1 BT BF BTCLR saddr.bit MOV1 BT BF BTCLR PSW.bit MOV1 BT BF BTCLR [HL].bit MOV1 BT BF BTCLR CY MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None
396
User's Manual U11302EJ4V0UM
CHAPTER 20
INSTRUCTION SET
(4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
Second Operand First Operand Basic instruction BR CALL BR CALLF CALLT BR BC BNC BZ BNZ Compound instruction BT BF BTCLR DBNZ AX !addr16 !addr11 [addr5] $addr16
(5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
User's Manual U11302EJ4V0UM
397
APPENDIX A DIFFERENCES BETWEEN PD78044H, 780228, AND 780208 SUBSERIES
Table A-1 shows the major differences between the PD78044H, 780228, and 780208 Subseries. Table A-1. Major Differences Between PD78044H, 780228, and 780208 Subseries
Part Number Item PROM or flash memory version
PD78044H Subseries PD78P048B (PROM)
VDD = 2.7 to 5.5 V
PD780228 Subseries PD78F0228 (flash memory)
VDD = 4.5 to 5.5 V
PD780208 Subseries PD78P0208 (PROM)
VDD = 2.7 to 5.5 V
Supply voltage Internal ROM size
PD78044H: PD78045H: PD78046H: PD78P048B:
32 40 48 60
KB KB KB KB
PD780226: 48 KB PD780228: 60 KB PD78F0228: 60 KB
PD780204: PD780204A: PD780205: PD780205A: PD780206: PD780208: PD78P0208:
32 32 40 40 48 60 60
KB KB KB KB KB KB KB
Internal expansion RAM size
PD78P048B only: 1024 bytes
512 bytes
PD780206, 780208, and 78P0208 only: 1024 bytes
64 bytes 80 bytes Main system clock or subsystem clock selectable 74 pins 53 pins 2 channels
Internal buffer RAM size VFD display RAM size CPU clock
PD78P048B only: 64 bytes
48 bytes Main system clock or subsystem clock selectable 68 pins 34 pins 1 channel 16-bit timer/event counter: 1 channel 8-bit timer/event counter: 2 channels Watch timer: 1 channel Watchdog timer: 1 channel Provided Provided
None 96 bytes Main system clock only
I/O ports Total of VFD display output pins Serial interface Timer
72 pins 48 pins
8-bit remote control timer: 1 channel 8-bit PWM timer: 2 channels Watchdog timer: 1 channel
16-bit timer/event counter: 1 channel 8-bit timer/event counter: 2 channels Watch timer: 1 channel Watchdog timer: 1 channel Provided Provided 11 4 Provided 100-pin plastic QFP (14 x 20)
Clock output Buzzer output Vectored interrupt source Test input Package Internal External
None None 8 4 None 100-pin plastic QFP (14 x 20)
10 4 Provided 80-pin plastic QFP (14 x 20)
Electrical specifications and Refer to individual data sheet. recommended soldering conditions
Remark In addition to the above items, the configuration of the development tools also differs between the above subseries (especially between the PROM and flash memory versions). For details, refer to the user's manual of each subseries.
398
User's Manual U11302EJ4V0UM
APPENDIX B
DEVELOPMENT TOOLS
The following development tools are available for the development of systems which employ the PD780208 Subseries. Figure B-1 shows the configuration of the development tools.
*
Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/ATTM compatible machines can be used for PC98NX series computers. When using PC98-NX series computers, refer to the description for IBM PC/AT compatible machines.
*
Windows Unless otherwise specified, "Windows" means the following OSs. * Windows 3.1 * Windows 95 * Windows 98 * Windows 2000 * Windows NTTM Ver. 4.0
User's Manual U11302EJ4V0UM
399
APPENDIX B
DEVELOPMENT TOOLS
Figure B-1. Configuration of Development Tools
Software package * Software package
Language processing software * Assembler package * C compiler package * Device file * C library source fileNote 1
Debugging software * Integrated debugger * System simulator
Control software * Project Manager (Windows only)Note 2 Embedded software * Real-time OS
Host machine (PC or EWS) Interface adapter, PC card interface, etc.
Power supply unit
PROM write environment PROM programmer
In-circuit emulator Emulation board
Programmer adapter
I/O board
On-chip PROM product
Performance board
Emulation probe
Conversion socket or conversion adapter Target system
Notes 1. The C library source file is not included in the software package. 2. The Project Manager is included in the assembler package. The Project Manager is only used for Windows.
400
User's Manual U11302EJ4V0UM
APPENDIX B
DEVELOPMENT TOOLS
B.1 Software Package
SP78K0 Software package This package contains various software tools for 78K/0 Series development. The following tools are included. RA78K0, CC78K0, ID78K0-NS, SM78K0, and various device files Part Number: SxxxxSP78K0
Remark xxxx in the part number differs depending on the OS used.
SxxxxSP78K0
xxxx AB17 BB17 Host Machine PC-9800 series, IBM PC/AT and compatibles OS Windows (Japanese version) Windows (English version) Supply Medium CD-ROM
B.2 Language Processing Software
RA78K0 Assembler package This assembler converts programs written in mnemonics into object codes executable with a microcontroller. Further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. This assembler should be used in combination with a device file (DF780208) (sold separately). This assembler package is a DOS-based application. It can also be used in Windows, however, by using the Project Manager (included in assembler package) in Windows. Part Number: SxxxxRA78K0 CC78K0 C compiler package This compiler converts programs written in C language into object codes executable with a microcontroller. This compiler should be used in combination with an assembler package and device file (both sold separately). This C compiler package is a DOS-based application. It can also be used in Windows, however, by using the Project Manager (included in assembler package) in Windows. Part Number: SxxxxCC78K0 DF780208Note 1 Device file This file contains information peculiar to the device. This device file should be used in combination with tools (RA78K0, CC78K0, SM78K0, ID78K0-NS, ID78K0, and RX78K0) (sold separately). The corresponding OS and host machine differ depending on the tool used. Part Number: SxxxxDF780208 CC78K0-LNote 2 C library source file This is a source file of functions configuring the object library included in the C compiler package. This file is required to match the object library included in C compiler package to the user's specifications. It does not depend on the operating environment because it is a source file. Part Number: SxxxxCC78K0-L
Notes 1. The DF780208 can be used in common with the RA78K0, CC78K0, SM78K0, ID78K0-NS, ID78K0, and RX78K0. 2. CC78K0-L is not included in the software package (SP78K0).
User's Manual U11302EJ4V0UM
401
APPENDIX B
DEVELOPMENT TOOLS
Remark xxxx in the part number differs depending on the host machine and OS used.
SxxxxRA78K0 SxxxxCC78K0
xxxx AB13 BB13 AB17 BB17 3P17 3K17 HP9000 series 700TM Host Machine PC-9800 series, IBM PC/AT and compatibles OS Windows (Japanese version) Windows (English version) Windows (Japanese version) Windows (English version) HP-UXTM (Rel. 10.10) SunOSTM (Rel. 4.1.4), SolarisTM (Rel. 2.5.1) CD-ROM Supply Medium 3.5-inch 2HD FD
SPARCstationTM
SxxxxDF780208 SxxxxCC78K0-L
xxxx AB13 BB13 3P16 3K13 3K15 Host Machine PC-9800 series, IBM PC/AT and compatibles HP9000 series 700 SPARCstation OS Windows (Japanese version) Windows (English version) HP-UX (Rel. 10.10) SunOS (Rel. 4.1.4), Solaris (Rel. 2.5.1) DAT 3.5-inch 2HD FD 1/4-inch CGMT Supply Medium 3.5-inch 2HD FD
B.3 Control Software
Project Manager This is control software designed to enable efficient user program development in the Windows environment. All operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from the Project Manager. The Project Manager is included in the assembler package (RA78K0). It can only be used in Windows.
402
User's Manual U11302EJ4V0UM
APPENDIX B
DEVELOPMENT TOOLS
B.4 PROM Programming Tools
B.4.1 Hardware
PG-1500 PROM programmer This PROM programmer allows users to encode the PROM in single-chip microcontrollers stand-alone or using a host machine. This requires connection of the accompanying board and separately-sold PROM programmer adapter to the PROM programmer. Besides internal PROMs, general discrete PROM devices whose capacities range from 256 Kb to 4 Mb can be programmed. This PROM programmer adapter is for the PD78P0208 and should be connected to the PG-1500. This adapter is for a 100-pin plastic QFP (GF-3BA type).
PA-78P0208GF PROM programmer adapter
B.4.2 Software
PG-1500 controller This software allows users to control the PG-1500 from a host machine which is connected to the PG-1500 via serial/parallel interface cable(s). Part Number: SxxxxPG1500
Remark xxxx in the part number differs depending on the host machine and OS used.
SxxxxPG1500
xxxx 5A13 5A10 7B13 7B10 IBM PC/AT and compatibles Host Machine PC-9800 series MS-DOS (Ver. 3.30 to Ver. 6.2 Note 2
Note 1
OS
Supply Medium 3.5-inch 2HD ) 5-inch 2HD 3.5-inch 2HD 5-inch 2HC
Notes 1. Although a task swap function is incorporated in MS-DOS Ver. 5.0 or later, this function cannot be used with the above software. 2. The following OSs for IBM PCs are supported (Ver. 5.0 or later of MSDOS has a task swap function, but this function cannot be used with the above software).
OS PC DOS Version Ver.5.02 to Ver.6.3 J6.1/V to J6.3/V (Only the English version is supported.) Ver.5.0 to Ver.6.22 5.0/V to 6.2/V (Only the English version is supported.) J5.02/V (Only the English version is supported.)
MS-DOS IBM DOSTM
User's Manual U11302EJ4V0UM
403
APPENDIX B
DEVELOPMENT TOOLS
B.5 Debugging Tools (Hardware)
B.5.1 When using in-circuit emulator IE-78K0-NS, IE-78K0-NS-A
IE-78K0-NS In-circuit emulator The in-circuit emulator serves to debug hardware and software when developing application systems using a 78K/0 Series product. It can be used with an integrated debugger (ID78K0-NS). This emulator should be used in combination with a power supply unit, emulation probe, and interface adapter, which is required to connect this emulator to the host machine. This board is used for extending the IE-78K0-NS functions. With the addition of this board, the addition of a coverage function, enhancement of tracer and timer functions, and other such debugging function enhancements are possible. In-circuit emulator that combines the IE-78K0-NS and IE-78K0-NS-PA This adapter is used for supplying power from a 100 to 240 V AC outlet.
IE-78K0-NS-PA Performance board
IE-78K0-NS-A In-circuit emulator IE-70000-MC-PS-B Power supply unit IE-70000-98-IF-C Interface adapter IE-70000-CD-IF-A PC card interface IE-70000-PC-IF-C Interface adapter IE-70000-PCI-IF-A Interface adapter IE-780208-NS-EM1 Emulation board NP-100GF-TQ NP-H100GF-TQ Emulation probe TGF-100RBP Conversion adapter NP-100GF Emulation probe EV-9200GF-100 Conversion socket (See Figures B-2 and B-3)
This adapter is required when using a PC-9800 series computer (except notebook type) as the IE-78K0-NS host machine (C bus compatible). This is the PC card and interface cable required when using a notebook-type computer as the IE-78K0-NS host machine (PCMCIA socket compatible). This adapter is required when using an IBM PC/AT compatible computer as the IE-78K0NS host machine (ISA bus compatible). This adapter is required when using a PC with a PCI bus as the IE-78K0-NS host machine. This board emulates the operations of the peripheral hardware peculiar to a device. It should be used in combination with an in-circuit emulator. This probe is used to connect the in-circuit emulator to the target system and is designed for a 100-pin plastic QFP (GF-3BA type). It should be used in combination with the TGF100RBP. This conversion socket connects the NP-100GF-TQ or NP-H100GF-TQ to the target system board designed to mount a 100-pin plastic QFP (GF-3BA type). This probe is used to connect the in-circuit emulator to the target system and is designed for a 100-pin plastic QFP (GF-3BA type). This conversion socket connects the NP-100GF to the target system board designed to mount a 100-pin plastic QFP (GF-3BA type).
Remarks 1. NP-100GF, NP-100GF-TQ, and NP-H100GF-TQ are products of Naito Densei Machida Mfg. Co., Ltd. Contact: Naito Densei Machida Mfg. Co., Ltd. +81-45-475-4191 2. TGF-100RBP is a product of TOKYO ELETECH CORPORATION. Inquiry: Daimaru Kogyo, Ltd. Phone: Tokyo Electronics Dept. 3. The EV-9200GF-100 is sold in a set of five units. 4. The TGF-100RBP is sold in single units. +81-3-3820-7112 Osaka Electronics 2nd Dept. +81-6-6244-6672
404
User's Manual U11302EJ4V0UM
APPENDIX B
DEVELOPMENT TOOLS
B.5.2 When using in-circuit emulator IE-78001-R-A
IE-78001-R-A In-circuit emulator This is an in-circuit emulator for debugging the hardware and software when an application system using the 78K/0 Series is developed. It can be used with an integrated debugger (ID78K0). This emulator is used with an emulation probe and interface adapter for connecting a host machine. This adapter is necessary when a PC-9800 series PC (except notebook type) is used as the host machine for the IE-78001-R-A (C bus compatible). This adapter is necessary when an IBM PC/AT or compatible machine is used as the host machine for the IE-78001-R-A (ISA bus compatible). This board is used with an in-circuit emulator to emulate device-specific peripheral hardware. This probe is for a 100-pin plastic QFP (GF-3BA type) and connects an in-circuit emulator and the target system. EV-9200GF-100 Conversion socket (See Figures B-2 and B-3) This conversion socket connects the board of the target system created to mount a 100-pin plastic QFP (GF-3BA type) and EP-78064GF-R.
IE-70000-98-IF-C Interface adapter IE-70000-PC-IF-C Interface adapter IE-780208-R-EM Emulation board EP-78064GF-R Emulation probe
Remark The EV-9200GF-100 is sold in a set of five units.
User's Manual U11302EJ4V0UM
405
APPENDIX B
DEVELOPMENT TOOLS
B.6 Debugging Tools (Software)
SM78K0 System simulator This is a system simulator for the 78K/0 Series. The SM78K0 is Windows-based software. It is used to perform debugging at the C source level or assembler level while simulating the operation of the target system on a host machine. Use of the SM78K0 allows the execution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development efficiency and software quality. The SM78K0 should be used in combination with a device file (DF780208) (sold separately). Part Number: SxxxxSM78K0 ID78K0-NS Integrated debugger (supporting in-circuit emulators IE-78K0-NS and IE-78K0-NS-A) ID78K0 Integrated debugger (supporting in-circuit emulator IE-78001-R-A) This debugger supports the in-circuit emulators for the 78K/0 Series. The ID78K0-NS is Windows-based software. It has improved C-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory display with the trace result. It should be used in combination with a device file (sold separately). Part Number: SxxxxID78K0-NS SxxxxID78K0
Remark xxxx in the part number differs depending on the host machine and OS used.
SxxxxSM78K0 SxxxxID78K0-NS SxxxxID78K0
xxxx AB13 BB13 AB17 BB17 Host Machine PC-9800 series, IBM PC/AT and compatibles OS Windows (Japanese version) Windows (English version) Windows (Japanese version) Windows (English version) CD-ROM Supply Medium 3.5-inch 2HD FD
406
User's Manual U11302EJ4V0UM
APPENDIX B
DEVELOPMENT TOOLS
B.7 Embedded Software
RX78K0 Real-time OS The RX78K0 is a real-time OS conforming to the ITRON specifications. A tool (configurator) for generating the nucleus of the RX78K0 and multiple information tables is supplied. Used in combination with an assembler package (RA78K0) and device file (DF780208) (both sold separately). The real-time OS is a DOS-based application. It should be used in the DOS prompt when using in Windows. Part Number: SxxxxRX78013-
Caution When purchasing the RX78K0, fill in the purchase application form in advance and sign the user agreement. Remark xxxx and in the part number differ depending on the host machine and OS used.
SxxxxRX78013-
001 100K 001M 010M S01 Source program Product Outline Evaluation object Mass-production object Maximum Number for Use in Mass Production Do not use for mass-produced product. 0.1 million units 1 million units 10 million units Source program for mass-produced object
xxxx AA13 AB13 BB13
Host Machine PC-9800 series IBM PC/AT and compatibles
OS Windows (Japanese version) Windows (Japanese version) Windows (English version)
Supply Medium 3.5-inch 2HD FD
User's Manual U11302EJ4V0UM
407
APPENDIX B
DEVELOPMENT TOOLS
B.8 Method for Upgrading from Former In-Circuit Emulator for 78K/0 Series to IE-78001-R-A
If you already have a former in-circuit emulator for 78K/0 Series microcontrollers (IE-78000-R or IE-78000-R-A), that in-circuit emulator can operate as an equivalent to the IE-78001-R-A by replacing its internal break board with the IE-78001-R-BK. Table B-1. Method for Upgrading from Former In-Circuit Emulator for 78K/0 Series to IE-78001-R-A
In-Circuit Emulator Owned IE-78000-R IE-78000-R-A In-Circuit Emulator Cabinet System-UpNote Required Not required Board to Be Purchased IE-78001-R-BK
Note
For upgrading a cabinet, send your in-circuit emulator to NEC Electronics.
408
User's Manual U11302EJ4V0UM
APPENDIX B
DEVELOPMENT TOOLS
B.9 Conversion Socket (EV-9200GF-100) Package Drawing and Recommended Footprint
Figure B-2. EV-9200GF-100 Package Drawing (for Reference Purposes only)
A B F M N
E
O
R D C S
K
EV-9200GF-100
1
No.1 pin index
P
G H I EV-9200GF-100-G0 ITEM A B C D E F G H I J K L M N O P Q R S MILLIMETERS 24.6 21 15 18.6 4-C 2 0.8 12.0 22.6 25.3 6.0 16.6 19.3 8.2 8.0 2.5 2.0 0.35 INCHES 0.969 0.827 0.591 0.732 4-C 0.079 0.031 0.472 0.89 0.996 0.236 0.654 076 0.323 0.315 0.098 0.079 0.014
2.3 1.5
0.091 0.059
Q
L
J
User's Manual U11302EJ4V0UM
409
APPENDIX B
DEVELOPMENT TOOLS
Figure B-3. Recommended Footprint for EV-9200GF-100 (for Reference Purposes only)
G
J K
F E D H
L
I
C B A EV-9200GF-100-P1 ITEM A B C D E F G H I J K L MILLIMETERS 26.3 21.6 INCHES 1.035 0.85
_0.002 0.650.02 x 29=18.850.05 0.026 +0.001 x 1.142=0.742+0.002 --0.002 _0.002 0.650.02 x 19=12.350.05 0.026 +0.001 x 0.748=0.486 +0.003 --0.002
15.6 20.3 12 0.05 6 0.05 0.35 0.02
2.36 0.03 2.3 1.57 0.03
0.614 0.799
_0.002 0.472 +0.003 _0.002 0.236 +0.003 _0.001 0.014 +0.001
0.093 +0.001 _0.002 0.091 0.062 +0.001 _0.002
Caution
The dimensions of the mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to the "Semiconductor Device Mount Manual" website (http://www.necel.com/pkg/en/mount/index.html).
410
User's Manual U11302EJ4V0UM
APPENDIX B
DEVELOPMENT TOOLS
B.10 Notes on Target System Design
The following shows the conditions when connecting the emulation probe to the conversion adapter. Follow the configuration below and consider the shape of parts to be mounted on the target system when designing a system. Among the products described in this appendix, the NP-100GF-TQ and NP-H100GF-TQ are products of Naito Densei Machida Mfg. Co., Ltd., and the TGF-100RBP is a product of TOKYO ELETECH CORPORATION. Table B-2. Distance Between IE System and Conversion Adapter
Emulation Probe Conversion Adapter Distance Between IE System and Conversion Adapter 170 mm 370 mm
NP-100GF-TQ NP-H100GF-TQ
TGF-100RBP
Figure B-4. Distance Between IE System and Conversion Adapter
In-circuit emulator IE-78K0-NS or IE-78K0-NS-A Target system Emulation board IE-780208-NS-EM1 170 mmNote
CN6
Emulation probe NP-100GF-TQ, NP-H100GF-TQ
Conversion adapter: TGF-100RBP
Note
Distance when the NP-100GF-TQ is used. When the NP-H100GF-TQ is used, the distance is 370 mm.
User's Manual U11302EJ4V0UM
411
APPENDIX B
DEVELOPMENT TOOLS
Figure B-5. Connection Conditions of Target System (When NP-100GF-TQ Is Used)
Emulation board IE-780208-NS-EM1 Emulation probe NP-100GF-TQ
Conversion adapter TGF-100RBP
11 mm
27.5 mm 40 mm
Pin 1
21 mm 34 mm
Target system
Figure B-6. Connection Conditions of Target System (When NP-H100GF-TQ Is Used)
Emulation board IE-780208-NS-EM1
Emulation probe NP-H100GF-TQ
Conversion adapter TGF-100RBP 27.5 mm Pin 1
11 mm
21 mm 45 mm
42 mm
Target system
412
User's Manual U11302EJ4V0UM
APPENDIX C
REGISTER INDEX
C.1 Register Index (by Register Name)
[A]
A/D conversion result register (ADCR) ... 192 A/D converter input select register (ADIS) ... 196 A/D converter mode register (ADM) ... 194 Automatic data transmit/receive address pointer (ADTP) ... 259 Automatic data transmit/receive control register (ADTC) ... 263, 274 Automatic data transmit/receive interval specification register (ADTI) ... 265, 275
[D]
Display mode register 0 (DSPM0) ... 104, 303 Display mode register 1 (DSPM1) ... 107, 303 Display mode register 2 (DSPM2) ... 304
[E]
8-bit compare register (CR10, CR20) ... 153 8-bit timer mode control register (TMC1) ... 155 8-bit timer output control register (TOC1) ... 156 8-bit timer register 1 (TM1) ... 153 8-bit timer register 2 (TM2) ... 153 External interrupt mode register (INTM0) ... 133, 343
[I]
Internal expansion RAM size switching register (IXS) ... 374 Internal memory size switching register (IMS) ... 372 Interrupt mask flag register 0H (MK0H) ... 341, 358 Interrupt mask flag register 0L (MK0L) ... 341 Interrupt request flag register 0H (IF0H) ... 340, 358 Interrupt request flag register 0L (IF0L) ... 340 Interrupt timing specification register (SINT) ... 216, 235, 252
[O]
Oscillation stabilization time select register (OSTS) ... 360
[P]
Port 0 (P0) ... 83 Port 1 (P1) ... 85 Port 2 (P2) ... 86 Port 3 (P3) ... 88 Port 7 (P7) ... 89 Port 8 (P8) ... 90 Port 9 (P9) ... 91 Port 10 (P10) ... 92
User's Manual U11302EJ4V0UM
413
APPENDIX C
REGISTER INDEX
Port 11 (P11) ... 93 Port 12 (P12) ... 94 Port mode register 0 (PM0) ... 95 Port mode register 1 (PM1) ... 95 Port mode register 2 (PM2) ... 95 Port mode register 3 (PM3) ... 95, 132, 157, 185, 189 Port mode register 7 (PM7) ... 95 Port mode register 10 (PM10) ... 95 Port mode register 11 (PM11) ... 95 Port mode register 12 (PM12) ... 95 Priority specification flag register 0H (PR0H) ... 342 Priority specification flag register 0L (PR0L) ... 342 Processor clock control register (PCC) ... 102 Program status word (PSW) ... 60, 346 Pull-up resistor option register (PUO) ... 97
[S]
Sampling clock select register (SCS) ... 134, 344 Serial bus interface control register (SBIC) ... 214, 220, 233, 251 Serial I/O shift register 0 (SIO0) ... 209 Serial I/O shift register 1 (SIO1) ... 259 Serial operating mode register 0 (CSIM0) ... 211, 218, 232, 250 Serial operating mode register 1 (CSIM1) ... 262, 269, 273 16-bit capture register (CR01) ... 126 16-bit compare register (CR00) ... 126 16-bit timer mode control register (TMC0) ... 129 16-bit timer output control register (TOC0) ... 131 16-bit timer register (TM0) ... 126 16-bit timer register (TMS) ... 153 Slave address register (SVA) ... 209
[T]
Timer clock select register 0 (TCL0) ... 127, 183 Timer clock select register 1 (TCL1) ... 153 Timer clock select register 2 (TCL2) ... 169, 177, 187 Timer clock select register 3 (TCL3) ... 211, 261
[W]
Watch timer mode control register (TMC2) ... 172 Watchdog timer mode register (WDTM) ... 179
414
User's Manual U11302EJ4V0UM
APPENDIX C
REGISTER INDEX
C.2 Register Index (by Register Symbol)
[A]
ADCR: ADIS: ADM: ADTC: ADTI: ADTP: A/D conversion result register ... 192 A/D converter input select register ... 196 A/D converter mode register ... 194 Automatic data transmit/receive control register ... 263, 274 Automatic data transmit/receive interval specification register ... 265, 275 Automatic data transmit/receive address pointer ... 259
[C]
CR00: CR01: CR10: CR20: CSIM0: CSIM1: 16-bit compare register ... 126 16-bit capture register ... 126 8-bit compare register ... 153 8-bit compare register ... 153 Serial operating mode register 0 ... 211, 218, 232, 250 Serial operating mode register 1 ... 262, 269, 273
[D]
DSPM0: Display mode register 0 ... 104, 303 DSPM1: Display mode register 1 ... 107, 303 DSPM2: Display mode register 2 ... 304
[I]
IF0H: IF0L: IMS: INTM0: IXS: Interrupt request flag register 0H ... 340, 358 Interrupt request flag register 0L ... 340 Internal memory size switching register ... 372 External interrupt mode register ... 133, 343 Internal expansion RAM size switching register ... 374
[M]
MK0H: MK0L: Interrupt mask flag register 0H ... 341, 358 Interrupt mask flag register 0L ... 341
[O]
OSTS: Oscillation stabilization time select register ... 360
[P]
P0: P1: P2: P3: P7: P8: P9: P10: P11: P12: Port 0 ... 83 Port 1 ... 85 Port 2 ... 86 Port 3 ... 88 Port 7 ... 89 Port 8 ... 90 Port 9 ... 91 Port 10 ... 92 Port 11 ... 93 Port 12 ... 94
User's Manual U11302EJ4V0UM
415
APPENDIX C
REGISTER INDEX
PCC: PM0: PM1: PM2: PM3: PM7: PM10: PM11: PM12: PR0H: PR0L: PSW: PUO:
Processor clock control register ... 102 Port mode register 0 ... 95 Port mode register 1 ... 95 Port mode register 2 ... 95 Port mode register 3 ... 95, 132, 157, 185, 189 Port mode register 7 ... 95 Port mode register 10 ... 95 Port mode register 11 ... 95 Port mode register 12 ... 95 Priority specification flag register 0H ... 342 Priority specification flag register 0L ... 342 Program status word ... 60, 346 Pull-up resistor option register ... 97
[S]
SBIC: SCS: SINT: SIO0: SIO1: SVA: Serial bus interface control register ... 214, 220, 233, 251 Sampling clock select register ... 134, 344 Interrupt timing specification register ... 216, 235, 252 Serial I/O shift register 0 ... 209 Serial I/O shift register 1 ... 259 Slave address register ... 209
[T]
TCL0: TCL1: TCL2: TCL3: TM0: TM1: TM2: TMC0: TMC1: TMC2: TMS: TOC0: TOC1: Timer clock select register 0 ... 127, 183 Timer clock select register 1 ... 153 Timer clock select register 2 ... 169, 177, 187 Timer clock select register 3 ... 211, 261 16-bit timer register ... 126 8-bit timer register 1 ... 153 8-bit timer register 2 ... 153 16-bit timer mode control register ... 129 8-bit timer mode control register ... 155 Watch timer mode control register ... 172 16-bit timer register ... 153 16-bit timer output control register ... 131 8-bit timer output control register ... 156
[W]
WDTM: Watchdog timer mode register ... 179
416
User's Manual U11302EJ4V0UM
APPENDIX D REVISION HISTORY
Here is the revision history of this manual. The "Applied to:" column indicates the chapters of each edition in which the revision was applied.
(1/2) Edition Second Revisions from Previous Edition * The following products are already developed: PD780204GF-xxx-3BA, Applied to: Throughout
PD780205GF-xxx-3BA, PD78P0208GF-xxx-3BA, PD78P0208KL-T
* Addition of the PD780206 and 780208 Change the power supply voltage values in 1.1 Features and 1.7 Function Outline Addition of the PD78018F, 78018FY, 78078, 78078Y, 78083, and 780208 Subseries on 1.5 78K/0 Series Expansion Addition of Caution about the condition of input leak current in 4.2.5 Port 7 CHAPTER 4 PORT FUNCTIONS Addition of Note on Table 4-3 Port Mode Register and Output Latch Setting when Alternate Function is Used Addition of 1/2 frequency divider on Figure 5-1 Clock Generator Block Diagram Addition of Note and Caution on Figure 9-3 Watchdog Timer Mode Register Format Deletion of CHAPTER 10 6-BIT UP/DOWN COUNTER CHAPTER 5 CLOCK GENERATOR CHAPTER 9 WATCHDOG TIMER CHAPTER 10 6-BIT UP/DOWN COUNTER Addition of Caution when using standby function on Figure 12-2 A/D Converter Mode Register Format Addition of Figure 12-11 AVDD Pin Connection Addition of Caution on 14.4.3 (3) (d) Busy control option CHAPTER 14 SERIAL INTERFACE CHANNEL 1 Correction of APPENDIX A DEVELOPMENT TOOLS Third The following products are already developed: PD780206GF-xxx-3BA, APPENDIX A DEVELOPMENT TOOLS Throughout CHAPTER 12 A/D CONVERTER CHAPTER 1 OUTLINE
PD780208GF-xxx-3BA
Addition of Quality Grade Correction of block diagrams of ports 2, 3, and 10 to 12 CHAPTER 1 OUTLINE CHAPTER 4 PORT FUNCTIONS CHAPTER 5 CLOCK GENERATOR CHAPTER 13 SERIAL INTERFACE CHANNEL 0
Change Caution when the external clock is input
Addition of Caution about changing operation mode of serial interface channel 0 Correction of Note on bit 7 (BSYE) of serial bus interface control register (SBIC) Addition of explanation of bus release signal, command signal, address, command, data, acknowledge signal, busy signal, and ready signal to the "Definition of SBI" Addition of Caution for the case that SB0 (SB1) line is changed when the SCK0 line is in high level in SBI mode
User's Manual U11302EJ4V0UM
417
APPENDIX D
REVISION HISTORY
(2/2) Edition Third Revisions from Previous Edition Correction of Cautions when the STOP mode is set Addition of APPENDIX A DIFFERENCES AMONG PD78044H, 780228, AND 780208 SUBSERIES Applied to: CHAPTER 17 STANDBY FUNCTION APPENDIX A DIFFERENCES AMONG PD78044H, 780228, AND 780208 SUBSERIES Throughout
Fourth
Addition of the following products to target products * PD780204A * PD780205A Deletion of the following package from target products * PD78P0208KL-T (100-pin ceramic WQFN) * Update of 1.6 78K/0 Series Lineup * Addition of Note in 1.8 Overview of Functions * Addition of Caution in Table 1-1 Mask Options in Mask ROM Versions * Addition of 2.2.12 VLOAD * Modification of Table 2-1 Types of Pin I/O Circuits * Addition of Caution in 3.1 Memory Space * Modification of Note in Table 3-3 Special-Function Register List * * * * * Addition Addition Addition Addition Addition of of of of of Caution Caution Caution Caution Caution in in in in in 4.2.6 Port 8 4.2.7 Port 9 4.2.8 Port 10 4.2.9 Port 11 4.2.10 Port 12
CHAPTER 1 OUTLINE
CHAPTER 2 PIN FUNCTIONS CHAPTER 3 CPU ARCHITECTURE CHAPTER 4 PORT FUNCTIONS
* Addition of Note in Figure 5-3 Format of Processor Clock Control Register * Modification of Caution in Figure 6-8 Format of External Interrupt Mode Register * Modification of 6.6 (5) Valid edge setting * Modification of Caution in Figure 8-2 Format of Timer Clock Select Register 2 * Modification of Caution in Figure 9-2 Format of Timer Clock Select Register 2 * Modification of Caution in Figure 11-2 Format of Timer Clock Select Register 2 * Addition of Caution in Figure 16-2 Format of Interrupt Request Flag Register * Modification of Caution in Figure 16-5 Format of External Interrupt Mode Register * Addition of description in Table 17-1 HALT Mode Operating Status * Addition of description in Table 17-3 STOP Mode Operating Status * Modification of Table 19-2 Internal Memory Size Switching Register Setting Values * Modification of description in Table A-1 Major Differences Between PD78044H, 780228, and 780208 Subseries
CHAPTER 5 CLOCK GENERATOR CHAPTER 6 16-BIT TIMER/EVENT COUNTER CHAPTER 8 WATCH TIMER CHAPTER 9 WATCHDOG TIMER CHAPTER 11 BUZZER OUTPUT CONTROLLER CHAPTER 16 INTERRUPT AND TEST FUNCTIONS CHAPTER 17 STANDBY FUNCTION CHAPTER 19 PD78P0208 APPENDIX A DIFFERENCES BETWEEN PD78044H, 780228, AND 780208 SUBSERIES APPENDIX B DEVELOPMENT TOOLS
* Modification of description
418
User's Manual U11302EJ4V0UM

▲Up To Search▲

Price & Availability of D780206GF

	To Download D780206GF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .